Skip to content
#

physical-verification

Star

Here is 1 public repository matching this topic...

KAMATHAM19 / RTL-to-GDSII-ASIC-design-of-Counter

Star 1

The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.

simulation routing rtl synthesis placement sta gdsii floorplan coverage-analysis powerplan physical-verification clock-tree-synthesis rc-extraction
  • Updated Jul 13, 2024
  • Tcl

Improve this page

Add a description, image, and links to the physical-verification topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the physical-verification topic, visit your repo's landing page and select "manage topics."

Learn more