v3.12.7

Option of using the new AXI Chip2Chip signal pins as per UW recommendation
Removed the requirement the RX startup FSM for CPLL lock to go down, because now the QPLL/CPLL reset outputs are driven by the user software instead
Stop GBT loopback counters when loopback is disabled
Trying to fix an issue with L1A propagation (removed double driver)

v3.12.4

NOTE: in this version all TTC commands from AMC13 are disabled by default and have to be enabled manually by writing 1 to GEM_AMC.TTC.CTRL.CMD_ENABLE

Features in this release:

• Fixed EMTF overlap link mapping (it is now link #2 instead of #6, it has to be that way due to EMTF patch panel)
• QPLL reset register added: GEM_AMC.OPTICAL_LINKS.MGT_CHANNEL_##.RESET.QPLL_RESET
• TTC command enable register added: GEM_AMC.TTC.CTRL.CMD_ENABLE
• GEMLoader firmware size register added (it is now disconnected from the UW GEMloader IP firmware size reg): GEM_AMC.GEM_SYSTEM.GEM_LOADER.FIRMWARE_SIZE

v3.12.3

CPLL power-down control added to the GTH control register (bit 7) - this should be used before resetting the CPLL

v3.12.2

L1A delay setting added. TTC module calibration mode is simplified - enabling calibration mode simply triggers the calpulse on L1A, and then the L1A can be delayed using the new delay setting

v3.12.1

v3.12.1 -- Sector ID register added that is used in the trigger TX to EMTF, also OH mask is now used in trigger TX; ipbus reset has been fixed and separated from the global reset register; legacy GLIB registers removed
v3.12.0 -- Changed the order of VFATs in GE2/1 to correspond to the silkscreen of the newest GEBs instead of the J number

v3.11.4

-- 3.11.1 Added an option to use HDLC VFAT addressing for GE2/1 (set GEM_AMC.GEM_SYSTEM.VFAT3.USE_VFAT_ADDRESSING to 1 to enable it)
-- 3.11.2 Added a GEM global reset register (recycled the unused GEM_SYSTEM.CNT_RESET address, renamed to GEM_AMC.GEM_SYSTEM.GLOBAL_RESET)
-- 3.11.3 Fixed a lockup problem when resetting the MMCM
-- 3.11.4 Introduced a CPLL reset control: bit 2 in the MGT reset reg (GEM_AMC.OPTICAL_LINKS.MGT_CHANNEL_XX.RESET.CPLL_RESET)

v3.11.0

Using jitter cleaned clock. Reworked TTC phase control and monitoring using DMTD. EMTF trigger links added.

===> NOTE: You should use the high bandwidth synthesizer configuration, which can be found in scripts/scripts/clkA_ttc_in_160p32_320p64_out_BW_HIGH.txt
For GE1/1 and GE2/1 update the cold boot script and replace the clockinit command line with this line:
clockinit clkA_ttc_in_160p32_320p64_out_BW_HIGH.txt 320_160 A0 A0 A0 A0

More details:
-- 3.9.11 Came back to using the MGT refclk as the source for all fabric clocks
-- 3.10.0 Reworked TTC clocking, added manual shifting possibility and phase monitoring (DMTD method used in TCDS), also bypassing the delay aligner in the GBT MGTs
-- 3.10.1 Reworked the phase alignment FSM to use the DMTD phase measurement instead of the PLL lock signal, this also allows for a configurable lock target phase and tollerance
-- 3.10.2 Trigger output links to EMTF added, using LpGBT ASIC TX encoding at 10.24Gb/s, and the protocol agreed with EMTF (note the RX side of these MGTs is still running at 3.2Gb/s to receive trigger data from OHs)
-- 3.11.0 Restructured MGTs to allow for easier configuration between different bus widths and usrclks. Now all MGT interfaces at the top level use 64 bit bus, and are remapped to appropriate bus sizes before connecting to gem_amc. The trigger TX MGT now uses 64 bit bus and 160MHz txusrclk2 to ease the timing

v3.9.10

====== Clocking ======
Backplane TTC clock is used as the source for all fabric clocks (note this version won't work without AMC13). Although setting the CFG_USE_BACKPLANE_CLK constant to false will revert to the old clocking where MGT refclk is the source for all fabric clocks, and TTC clock is only used to align the phase (phase align can be switched off with a register called GEM_AMC.OPTICAL_LINKS.DISABLE_TTC_PHASE_ALIGN, which can be used for operation without AMC13).

In terms of operation, having the backplane TTC clock as the source is easier to manage because there's no need to worry about the phase drift, but on the other hand if the TTC clock is lost or has an abrupt phase jump, the optical links can get messed up and will need a reset. Optical link reset can be done by writing 1 to GEM_AMC.OPTICAL_LINKS.MGT_CHANNEL_.RESET.TX_RESET and GEM_AMC.OPTICAL_LINKS.MGT_CHANNEL_.RESET.RX_RESET, or simply write 3 to GEM_AMC.OPTICAL_LINKS.MGT_CHANNEL_*.RESET.
So when using this version, it is recommended that the MGT reset is done during every RCMS configure transition.

====== General ======
GEM_AMC.GEM_SYSTEM.RELEASE.GEM_STATION provides the station number of the build (0 = ME0, 1 = GE1/1, 2 = GE2/1)

if a GBT ready goes low, all VFATs from that GBT are automatically masked (and unmasked when ready again). Removed unused register: USE_OH_VFAT3_SLOTS

Added registers to report the promless loaded statistics:
GEM_AMC.GEM_SYSTEM.GEM_LOADER.LOAD_REQUEST_CNT
GEM_AMC.GEM_SYSTEM.GEM_LOADER.LOAD_SUCCESS_CNT
GEM_AMC.GEM_SYSTEM.GEM_LOADER.LOAD_FAIL_CNT
GEM_AMC.GEM_SYSTEM.GEM_LOADER.STREAM_GAP_CNT
GEM_AMC.GEM_SYSTEM.GEM_LOADER.LOADER_OVF_UNF_CNT

PRBS loopback test added, which is looping through all elinks of all GBTs. This is most useful for GE2/1 OHv2 since it has lots of elinks connected to the FPGA.

====== GE2/1 ======
Optical link mapping has changed: previously was the same as GE1/1, meaning that GBT2 link was still there but supposed to be not connected. Now the GE2/1 only has GBT0 and GBT1, so OH0 connects to links 1 and 2, OH1 connects to links 3 and 4, etc...

V2 OptoHybrid is also supported, but requires a separate ctp7 firmware due to the use of wide-bus mode on GBT1. So there will be 2 CTP7 firmwares labeled ge21v1 and ge21v2 as the station.

SCA config is correct by default. Hard resets should work automatically, so no need to hard-reset the OH FPGA using SCA manual GPIO control.

====== ME0 ======
Support for LpGBT and ME0 has been added. The firmware has been fully verified with the ME0 ASIAGO v1 board + PIZZA on the GE2/1 detector. We confirmed communication to all VFATs, and were able to take scurve scans. LpGBT IC also has been verified to work (both for the master and slave chips).
Trigger data has not been extensively tested yet.

v3.9.0

DAQ input processor now supports variable width VFAT data (though this will still have to be optimized for better resource utilization)

Calibration mode data format added - it's a very aggressive bandwidth saving mode designed for calibration runs, which drops most of the VFAT data, except for the VFAT position, 2 bits of EC, and just one channel bit for the selected channel number, so each VFAT only takes up 8 bits. Note: addresses of existing DAQ registers have been changed in order to accommodate the new registers, so it's necessary to update the address table for this version.

Calibration format details:

• the calibration format can be turned on and off with GEM_AMC.DAQ.CONTROL.CALIBRATION_MODE_EN register, and the VFAT channel is selected by GEM_AMC.DAQ.CONTROL.CALIBRATION_MODE_CHAN register.
• The data format has been updated according to v301 sheet in this spreadsheet: https://docs.google.com/spreadsheets/d/1iKMl68vMsSWgr8ekVdsJYTk7-Pgy8paxq98xj6GtoVo/edit?ts=5bf03401#gid=929454128
  • only unused space is utilized, so it's not a problem for old unpacker software
  • GEM Event Header now uses bits [10:8] for P_VERSION (payload version), and bits [7:4] for P_TYPE (payload type). When running in default format mode these fields are set to 0, and in calibration mode the the P_TYPE is set to 0xF, and P_VERSION is kept at 0.
  • GEM Chamber Header now uses bits [46:40] to indicate the selected calibration channel
  • When in calibration mode, each VFAT block consists of just 8 bits where bit 7 contains the hit data for the selected channel, bits [6:5] contain the two lowest bits of EC, and bits [4:0] contain the VFAT position
  • The VfWdCnt in the Chamber Header still shows the number of VFAT payload 64bit words, and this many 64bit words must be read out
  • The VFAT 8bit words are filled in the 64bit VFAT payload words starting at the top bit (63), and any unused lower bits in the last 64bit word of the VFAT payload section are filled with 1. So when attempting to read a VFAT block in the unused/filled section of the last 64bit word will result in VFAT position being binary 11111 = 31, which is an invalid position and should signal to the unpacker that there are no more VFAT blocks in this 64bit word.

v3.8.6

Fixing a loophole in the DAQ input processor module: previously a condition existed for event word count to be lower by one VFAT if a new event came exactly at the clock cycle when the old one timed out, which could result in an offset of the input data from that point on, and show up as VFAT packet from a previous event. Hopefully this will solve the EC/BC mismatch problem seen at GE1/1 QC8 cosmic stand.

Also v3.8.5 fixed a small bug in the OH slow control TX FSM, where the state of some control signals was not defined during reset, which may result in some valid-looking slow control commands being spit out to the OH when doing a link reset, even though the FSM should just send out idles. There's no real proof that this ever happened, but it might.

OH address table was updated to the latest one for the generated UHAL XMLs. The UHAL XMLs will use a module node in future versions.