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Merge pull request #19 from evka85/v3
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V3
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@evka85
evka85 committed Jul 16, 2020
2 parents 72df462 + 0143f21 commit 9b70a09
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Showing 110 changed files with 10,537 additions and 1,868 deletions.
4 changes: 2 additions & 2 deletions common/hdl/daq/daq.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -1106,7 +1106,7 @@ begin
x"000000" & -- Chamber error flag (hmm)
-- GLIB status
daq_almost_full &
ttc_status_i.mmcm_locked &
ttc_status_i.clk_status.mmcm_locked &
daq_clk_locked_i &
daq_ready &
ttc_status_i.bc0_status.locked &
Expand Down Expand Up @@ -1358,7 +1358,7 @@ begin
regs_read_arr(3)(REG_DAQ_EXT_CONTROL_RUN_TYPE_MSB downto REG_DAQ_EXT_CONTROL_RUN_TYPE_LSB) <= run_type;
regs_read_arr(4)(REG_DAQ_STATUS_DAQ_LINK_RDY_BIT) <= daq_ready;
regs_read_arr(4)(REG_DAQ_STATUS_DAQ_CLK_LOCKED_BIT) <= daq_clk_locked_i;
regs_read_arr(4)(REG_DAQ_STATUS_TTC_RDY_BIT) <= ttc_status_i.mmcm_locked;
regs_read_arr(4)(REG_DAQ_STATUS_TTC_RDY_BIT) <= ttc_status_i.clk_status.mmcm_locked;
regs_read_arr(4)(REG_DAQ_STATUS_DAQ_LINK_AFULL_BIT) <= daq_almost_full;
regs_read_arr(4)(REG_DAQ_STATUS_DAQ_OUTPUT_FIFO_HAD_OVERFLOW_BIT) <= err_daqfifo_full;
regs_read_arr(4)(REG_DAQ_STATUS_TTC_BC0_LOCKED_BIT) <= ttc_status_i.bc0_status.locked;
Expand Down
6 changes: 3 additions & 3 deletions common/hdl/gbt_bank/gbt.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -79,8 +79,8 @@ entity gbt is
--========--

mgt_rx_rdy_arr_i : in std_logic_vector(NUM_LINKS - 1 downto 0);
mgt_tx_data_arr_o : out t_gt_gbt_data_arr(NUM_LINKS - 1 downto 0);
mgt_rx_data_arr_i : in t_gt_gbt_data_arr(NUM_LINKS - 1 downto 0);
mgt_tx_data_arr_o : out t_std40_array(NUM_LINKS - 1 downto 0);
mgt_rx_data_arr_i : in t_std40_array(NUM_LINKS - 1 downto 0);

--===========--
-- Status --
Expand Down Expand Up @@ -152,7 +152,7 @@ architecture gbt_arch of gbt is
signal rxHeaderLocked_from_gbtRx : std_logic_vector(NUM_LINKS - 1 downto 0);

signal rx_common_word_clk : std_logic;
signal mgt_sync_rx_data_arr : t_gt_gbt_data_arr(NUM_LINKS - 1 downto 0);
signal mgt_sync_rx_data_arr : t_std40_array(NUM_LINKS - 1 downto 0);
signal mgt_sync_rx_valid_arr : std_logic_vector(NUM_LINKS - 1 downto 0);

signal rx_data_arr : t_gbt_frame_array(NUM_LINKS - 1 downto 0);
Expand Down
58 changes: 47 additions & 11 deletions common/hdl/gem_amc.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -41,24 +41,27 @@ entity gem_amc is
reset_pwrup_o : out std_logic;

-- TTC
ttc_clocks_i : in t_ttc_clks;
ttc_clocks_locked_i : in std_logic;
ttc_clocks_i : in t_ttc_clks;
ttc_clk_status_i : in t_ttc_clk_status;
ttc_clk_ctrl_o : out t_ttc_clk_ctrl;
ttc_data_p_i : in std_logic; -- TTC protocol backplane signals
ttc_data_n_i : in std_logic;

-- Trigger RX GTX / GTH links (3.2Gbs, 16bit @ 160MHz w/ 8b10b encoding)
gt_trig0_rx_clk_arr_i : in std_logic_vector(g_NUM_OF_OHs - 1 downto 0);
gt_trig0_rx_data_arr_i : in t_gt_8b10b_rx_data_arr(g_NUM_OF_OHs - 1 downto 0);
gt_trig0_rx_data_arr_i : in t_mgt_16b_rx_data_arr(g_NUM_OF_OHs - 1 downto 0);
gt_trig1_rx_clk_arr_i : in std_logic_vector(g_NUM_OF_OHs - 1 downto 0);
gt_trig1_rx_data_arr_i : in t_gt_8b10b_rx_data_arr(g_NUM_OF_OHs - 1 downto 0);
gt_trig1_rx_data_arr_i : in t_mgt_16b_rx_data_arr(g_NUM_OF_OHs - 1 downto 0);

-- Trigger TX GTH links (3.2Gbs, 16bit @ 160MHz w/ 8b10b encoding) -- this is just for testing right now, will be changed to (9.6Gbs, 32bit @ 240MHz w/ 8b10b encoding)
gt_trig_tx_data_arr_o : out t_gt_8b10b_tx_data_arr(g_NUM_TRIG_TX_LINKS - 1 downto 0);
-- Trigger TX GTH links (10.24Gbs, 32bit @ 320MHz with LpGBT encoding)
gt_trig_tx_data_arr_o : out t_std64_array(g_NUM_TRIG_TX_LINKS - 1 downto 0);
gt_trig_tx_clk_i : in std_logic;
gt_trig_tx_status_arr_i : in t_mgt_status_arr(g_NUM_TRIG_TX_LINKS - 1 downto 0);
trig_tx_data_raw_arr_o : out t_std234_array(g_NUM_TRIG_TX_LINKS - 1 downto 0); -- this raw data before lpgbt encoding, and is only meant for debugging

-- GBT DAQ + Control GTX / GTH links (4.8Gbs, 40bit @ 120MHz without encoding when using GBTX, and 10.24Gbp, lower 32bit @ 320MHz without encoding when using LpGBT)
gt_gbt_rx_data_arr_i : in t_gt_gbt_data_arr(g_NUM_OF_OHs * g_NUM_GBTS_PER_OH - 1 downto 0);
gt_gbt_tx_data_arr_o : out t_gt_gbt_data_arr(g_NUM_OF_OHs * g_NUM_GBTS_PER_OH - 1 downto 0);
gt_gbt_rx_data_arr_i : in t_std40_array(g_NUM_OF_OHs * g_NUM_GBTS_PER_OH - 1 downto 0);
gt_gbt_tx_data_arr_o : out t_std40_array(g_NUM_OF_OHs * g_NUM_GBTS_PER_OH - 1 downto 0);
gt_gbt_rx_clk_arr_i : in std_logic_vector(g_NUM_OF_OHs * g_NUM_GBTS_PER_OH - 1 downto 0);
gt_gbt_tx_clk_arr_i : in std_logic_vector(g_NUM_OF_OHs * g_NUM_GBTS_PER_OH - 1 downto 0);
gt_gbt_rx_common_clk_i : in std_logic;
Expand Down Expand Up @@ -161,6 +164,7 @@ architecture gem_amc_arch of gem_amc is
--== Trigger signals ==--
signal sbit_clusters_arr : t_oh_sbits_arr(g_NUM_OF_OHs - 1 downto 0);
signal sbit_links_status_arr : t_oh_sbit_links_arr(g_NUM_OF_OHs - 1 downto 0);
signal emtf_data_arr : t_std234_array(g_NUM_TRIG_TX_LINKS - 1 downto 0);

--== GBT ==--
signal gbt_tx_data_arr : t_gbt_frame_array(g_NUM_OF_OHs * g_NUM_GBTS_PER_OH - 1 downto 0);
Expand Down Expand Up @@ -301,7 +305,8 @@ begin
port map(
reset_i => reset,
ttc_clks_i => ttc_clocks_i,
ttc_clks_locked_i => ttc_clocks_locked_i,
ttc_clks_status_i => ttc_clk_status_i,
ttc_clks_ctrl_o => ttc_clk_ctrl_o,
ttc_data_p_i => ttc_data_p_i,
ttc_data_n_i => ttc_data_n_i,
ttc_cmds_o => ttc_cmd,
Expand Down Expand Up @@ -430,14 +435,45 @@ begin
sbit_clusters_i => sbit_clusters_arr,
sbit_link_status_i => sbit_links_status_arr,
trig_led_o => led_trigger_o,
tx_link_clk_i => gt_trig_tx_clk_i,
trig_tx_data_arr_o => gt_trig_tx_data_arr_o,
trig_tx_data_arr_o => emtf_data_arr,
ipb_reset_i => ipb_reset,
ipb_clk_i => ipb_clk_i,
ipb_miso_o => ipb_miso_arr(C_IPB_SLV.trigger),
ipb_mosi_i => ipb_mosi_arr_i(C_IPB_SLV.trigger)
);

--================================--
-- EMTF Transmitters (LpGBT TX)
--================================--

g_emtf_links_enabled : if g_USE_TRIG_TX_LINKS generate
g_emtf_links : for i in 0 to g_NUM_TRIG_TX_LINKS - 1 generate

i_emtf_lpgbt_tx : entity work.lpgbt_10g_tx
generic map (
g_MGT_TX_BUS_WIDTH => 64,
g_TXUSRCLK_TO_TTC40_RATIO => 4
)
port map(
reset_i => reset,
clk40_i => ttc_clocks_i.clk_40,
mgt_tx_usrclk_i => gt_trig_tx_clk_i,
mgt_tx_ready_i => gt_trig_tx_status_arr_i(i).tx_reset_done,
mgt_tx_data_o => gt_trig_tx_data_arr_o(i),
tx_data_i => emtf_data_arr(i),
tx_ready_o => open,
tx_had_not_ready_o => open
);

end generate;
end generate;

trig_tx_data_raw_arr_o <= emtf_data_arr;

g_emtf_links_disabled : if not g_USE_TRIG_TX_LINKS generate
gt_trig_tx_data_arr_o <= (others => (others => '0'));
end generate;

--================================--
-- ME0 Trigger
--================================--
Expand Down
14 changes: 11 additions & 3 deletions common/hdl/lpgbt/gearbox/txgearbox.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,8 @@ entity txGearbox is
generic (
c_clockRatio : integer; --! Clock ratio is clock_out / clock_in (shall be an integer)
c_inputWidth : integer; --! Bus size of the input word
c_outputWidth : integer --! Bus size of the output word (Warning: c_clockRatio/(c_inputWidth/c_outputWidth) shall be an integer)
c_outputWidth : integer; --! Bus size of the output word (Warning: c_clockRatio/(c_inputWidth/c_outputWidth) shall be an integer)
c_reset_dly : integer := 0
);
port (
-- Clock and reset
Expand Down Expand Up @@ -51,8 +52,10 @@ architecture behavioral of txGearbox is

signal gearboxSyncReset : std_logic;
signal rst_gearbox_s : std_logic;
signal rst_gearbox_dly_s : integer := c_reset_dly;

signal txFrame_from_frameInverter_s : std_logic_vector (c_inputWidth-1 downto 0);
signal txFrame_from_frameInverter_pipe0_s : std_logic_vector (c_inputWidth-1 downto 0);
signal txFrame_from_frameInverter_pipe_s : std_logic_vector (c_inputWidth-1 downto 0);
signal in_txFrame_from_frameInverter_s : std_logic_vector (c_inputWidth-1 downto 0);
signal txFrame_from_frameInverter_reg_s : std_logic_vector (c_inputWidth-1 downto 0);
Expand Down Expand Up @@ -85,10 +88,14 @@ begin --========#### Architecture Body ####========--
begin
if rst_gearbox_i = '1' then
rst_gearbox_s <= '1';
rst_gearbox_dly_s <= rst_gearbox_dly_s;

elsif rising_edge(clk_inClk_i) then
if clk_clkEn_i = '1' then
if clk_clkEn_i = '1' and rst_gearbox_dly_s = 0 then
rst_gearbox_s <= '0';
rst_gearbox_dly_s <= 0;
elsif clk_clkEn_i = '1' then
rst_gearbox_dly_s <= rst_gearbox_dly_s - 1;
end if;
end if;
end process;
Expand All @@ -106,7 +113,8 @@ begin --========#### Architecture Body ####========--
pipeline_proc: process(clk_outClk_i)
begin
if rising_edge(clk_outClk_i) then
txFrame_from_frameInverter_pipe_s <= in_txFrame_from_frameInverter_s;
txFrame_from_frameInverter_pipe0_s <= in_txFrame_from_frameInverter_s;
txFrame_from_frameInverter_pipe_s <= txFrame_from_frameInverter_pipe0_s;
end if;
end process;

Expand Down
4 changes: 2 additions & 2 deletions common/hdl/lpgbt/lpgbt.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,8 @@ entity lpgbt is

mgt_status_arr_i : in t_mgt_status_arr(g_NUM_LINKS - 1 downto 0);
mgt_ctrl_arr_o : out t_mgt_ctrl_arr(g_NUM_LINKS - 1 downto 0);
mgt_tx_data_arr_o : out t_gt_gbt_data_arr(g_NUM_LINKS - 1 downto 0); -- only 32 out of the 40 bits are used
mgt_rx_data_arr_i : in t_gt_gbt_data_arr(g_NUM_LINKS - 1 downto 0); -- only 32 out of the 40 bits are used
mgt_tx_data_arr_o : out t_std40_array(g_NUM_LINKS - 1 downto 0); -- only 32 out of the 40 bits are used
mgt_rx_data_arr_i : in t_std40_array(g_NUM_LINKS - 1 downto 0); -- only 32 out of the 40 bits are used

--========--
-- GBT TX --
Expand Down
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