v1.1.6

Fix broken cherry-pick 1dcf990 - bad regUpdate code

v1.1.5

Re-apply #859 (allowing overrides to $random) to fix v1.1.4 regression.

v1.1.4

This release add the following bug fixes and features:

• Combine cats (#851)
• Add FIRRTL logo to repo and README (#938)
• Update commandline sbt publishLocal (#931)
• Don't include verilog header files in "FileList" for VCS/Verilator. (#918)
• Fix $TRAVIS_COMMIT_RANGE (#927)
• Fix TRAVIS_COMMIT_RANGE in .run_chisel_tests, replace ... with .. (#924)
• Better error message on missing BlackBox resource (#921)
• Added reference to ICCAD paper (#915)
• Number all code examples & add specification build to Makefile (#894)
• Add Utils.expandPrefixes as Prefix Unique helper (#900)
• Enforce port uniqueness in Chirrtl/High Checks (#898)
• Another TopWiring Bug Fix (Multi-Level Annotations) (#889)
• Add CODEOWNERS file (#895)
• Do not remove ExtMods with no ports by default (#888)
• Bump scopt from 3.6.0 -> 3.7.0 (#875)
• Filter resource file names to avoid including the same file multiple times. (#883)
• Make Scala 2.12.4 the default. (#848)
• Binding support - load memory from file (#854)
• Support for load memory annotations in chisel (#833)
• Bump ANTLR version and change directory to play nice with IntelliJ (#824)
• Make InstanceGraph have deterministic and use defined iteration order (#843)
• Cleaning up BlackBoxSourceHelper (#786)
• Add utilities for UInt and SInt literals (#815)

v1.1.3

This release adds the following bug fixes and features:

• Bug Fixes in TopWiring (#885)
• Add explicit SystemVerilogCompiler class (#878)
• Update DontTouchAnnotation not found error message (#864)
• Fix NoDedupMem to be cognizant of Module scope (#876)
• Add LogLevel apply for String => LogLevel.Value (#877)
• Allow the #delay before random initialization to be overridden (#872)
• Add targetDirName test (#869)
• allowing overrides to $random (#859)
• Make RemoveWires properly include registers in dependency graph (#868)
• add link to repo for firrtl syntax highlighting in sublime text 3 (#861)
• Fix Travis - add $HOME/.sbt to cache(#858)
• Use LinkedHashSet in propagateAnnotations (#855)
• Constant prop add (#849)
• Replace unconnected registers with 0 in Constant Propagation (#776)
• Adding the firrtl proto. (#746)

v1.1.2

This release candidate includes the following bug fixes and performance improvements:

• Fix bug in zero-width renaming (#845)
• Combinational Dependency Annotation (#809)
• InferWidths: improve performance (#846)
• Missing match on PassExceptions fixed. (#844)
• Improve code generation for smem wmode and [w]mask ports (#834)
• Make ZeroWidth properly rename removed empty aggregates (#839)
• Make CheckCombLoops find combinational nodes with self-edges (#837)
• Remove checkboxes from issue/pr templates (#826)
• Provide a ProcessLogger() to capture all output in isCommandAvailable(). (#831)

v1.1.1

This release candidate includes the following bug fixes and performance improvements:

• Improve Parser and Visitor (#819)
• Fix TopWiringTests use of /tmp. (#825)
• Resolve register clock dependencies in RemoveWires (#823)
• Deprecate SingleStringAnnotation (#811)
• Allow escaped single quotes in RawParams (#820)
• Use attach to connect analogs when grouping (#805)
• Fix some typos in leftovers.txt (#822)
• ucb-bar -> freechipsproject in clone instruction
• Add a blacklist option for paths (#810)
• Mechanism to stop verilator from generating VCD file Chisel Issue #808 (#794)
• ConstProp attached wires if there is also a port (#818)
• Improve Travis configuration (#816)
• Makes ExpandWhens preserve connect Infos (#816)
• Fix pad (#817)
• Add Circuit as option to FirrtlOptions (#814)
• Fix more problems with zero width things. (#779)
• Bump version of Verilator used in Travis to 3.922 (#784)
• Don't use bash to determine command availability - fixes #807 (#808)
• Replace truncating add and sub with addw/subw (#800)
• TopWiring Transform (#798)
• Bugfix: ports of a temporary name would break const-prop (#806)
• Deprecate old WiringUtils methods/classes (#801)
• Fix pathological behavior of Namespace for name collisions (#788)
• Fix bug in VerilogMemDelays (#795)
• Cleaning up BlackBoxSourceHelper - use absolute file paths. (#789)
• Remove infinitely recursive function (#790)
• Make DiGraph.linearize be iterative instead of recursive (#785)
• Fix bug in Constant Propagation for registers propped to zero (#787)
• Make Dedup properly dedup ExtModules (#781)
• CyclicException identifies a problem node. (#778)
• Enhance RenameMap to support circuit renaming (#775)
• Change throwInternalError to use a String instead of Option[String] (#777)
• Const prop improvement (#772)
• Make WiringTransform remove its used annotations (#774)
• Better bad annotation file error reporting (#771)
• GroupModule Transform (#766)
• Add SyntaxErrorsException as a type of ParserException (#770)
• Correct extmodule example in spec (#768)
• Pass up annotations in return value from Driver.execute (#760)
• Update README.md (#761)
• Masks for zero-width fields of mems should be width zero. (#763)
• Improve section heading (#762)
• Reduce Statement nesting in Wiring Pass (#751)
• Fix annotation deserialization of component subfields (#750)

v1.1.0

This release incorporates changes from v1.1.0-RC1 and v1.1.0-RC2. Please see the release notes from those candidates.

v1.1.0-RC1

This release includes the following backward incompatible API changes:

• Rename loadAnnotations -> getAnnotations (#747)
• Rename LsbLargerThanMsb to LsbLargerThanMsbException (#740)
• Refactor Annotations (#721)
• Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, but not Emitter. (#717)
• Refactor Annotations Driver API (#704)
  • Fix FirrtlExecutionOptions backward incompatible change (#704). (#720)
  • Add support for multiple annotation files
  • Actually emit annotations as YAML instead of default toString
  • Remove option --force-append-anno-file, make default
  • Add Driver.dramaticWarning
• out-of-bounds vec accesses now invalid, not first element (#685)
• Change primop arg type (#587)

If you are using your own build and execution harness that does not use one of the the Driver.execute family you may need to explicitly load annotations into memory and then set the annotations field of the optionsManager.firrtlOptions. For an example, see lines 124-125 of chisel-testers/src/main/scala/chisel3/iotesters/FirrtlTerpBackend.scala.

This release includes the following bug and typo fixes:

• Add log-level debug message for modules that get deduped (#748)
• Add graph summation "+" to DiGraph (#744)
• Fix EulerTour for circuits with one module (#736)
• Make Constant Propagation respect dontTouch on registers (#735)
• CheckHighForm should check that Bits MSB >= LSB (#700)
• Update spec for rhs (#450)
• Replacematcherror - catch exceptions and convert to internal error. (#424)
• Fix typo: ExecutionOptionManager -> ExecutionOptionsManager. (#724)
• Remove erroneous undef of RANDOMIZE in emitted Verilog (#723)
• Adjust isVCSAvailable comment (#715)
• Spec erroneously says mod instead of rem. (#713)

This release includes the following new features:

• Bump sbt to 1.1.1 and bump plugins (#739)
• Add firrtl-mode to README.md (#730)
• Added comments to ExpandWhens (#716)
• WiringTransform Refactor (#647)
• Add logger printing for declarations removed by DCE (#612)
• Add NodeCount analysis for helping with performance debugging (#637)
• Removed top preamble (#640)

v1.0.2

This release of firrtl includes bug fixes for the following issues:

• Fix Bugs in Constant Propagation (#735)

v1.0.1

firrtl Release Notes

This release of firrtl includes bug fixes for the following issues:

• AnnotationUtils.toNamed broken (#708)
• submodule inputs aren't correctly invalidated in conditionals (#705)
• bug in ConstProp where module dependency edges were dropped (#696)
• annotating a module IO with DontTouch that will get de-duplicated fails (#689)
• Dedup does not do any renaming (#593)
• shl(x, -1) should issue an error (#527)
• SystemVerilog 2009 reserved word not implemented: checker (#455)

Additionally, we added:

• support -X sverilog to output xxxx.sv file (#638)
• getBuildDir now builds full path (#652)
• several internal checks and improvements (#684)
• add alternative graph IR (#671)