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v1.1.0-RC1

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@ucbjrl ucbjrl released this 06 Mar 20:58
v1.1.0-RC1
7b78723

This release includes the following backward incompatible API changes:

  • Rename loadAnnotations -> getAnnotations (#747)
  • Rename LsbLargerThanMsb to LsbLargerThanMsbException (#740)
  • Refactor Annotations (#721)
  • Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, but not Emitter. (#717)
  • Refactor Annotations Driver API (#704)
    • Fix FirrtlExecutionOptions backward incompatible change (#704). (#720)
    • Add support for multiple annotation files
    • Actually emit annotations as YAML instead of default toString
    • Remove option --force-append-anno-file, make default
    • Add Driver.dramaticWarning
  • out-of-bounds vec accesses now invalid, not first element (#685)
  • Change primop arg type (#587)

If you are using your own build and execution harness that does not use one of the the Driver.execute family you may need to explicitly load annotations into memory and then set the annotations field of the optionsManager.firrtlOptions. For an example, see lines 124-125 of chisel-testers/src/main/scala/chisel3/iotesters/FirrtlTerpBackend.scala.

This release includes the following bug and typo fixes:

  • Add log-level debug message for modules that get deduped (#748)
  • Add graph summation "+" to DiGraph (#744)
  • Fix EulerTour for circuits with one module (#736)
  • Make Constant Propagation respect dontTouch on registers (#735)
  • CheckHighForm should check that Bits MSB >= LSB (#700)
  • Update spec for rhs (#450)
  • Replacematcherror - catch exceptions and convert to internal error. (#424)
  • Fix typo: ExecutionOptionManager -> ExecutionOptionsManager. (#724)
  • Remove erroneous undef of RANDOMIZE in emitted Verilog (#723)
  • Adjust isVCSAvailable comment (#715)
  • Spec erroneously says mod instead of rem. (#713)

This release includes the following new features:

  • Bump sbt to 1.1.1 and bump plugins (#739)
  • Add firrtl-mode to README.md (#730)
  • Added comments to ExpandWhens (#716)
  • WiringTransform Refactor (#647)
  • Add logger printing for declarations removed by DCE (#612)
  • Add NodeCount analysis for helping with performance debugging (#637)
  • Removed top preamble (#640)
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