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FIRRTL cherry-pick 833/859 fix
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Merge branch '1.1.x' into 1.1.5
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ucbjrl committed Dec 14, 2018
2 parents 534de61 + 8f2ce70 commit 8d4e01b
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Showing 2 changed files with 9 additions and 3 deletions.
2 changes: 1 addition & 1 deletion build.sbt
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ organization := "edu.berkeley.cs"

name := "firrtl"

version := "1.1.4"
version := "1.1.5"

scalaVersion := "2.12.4"

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10 changes: 8 additions & 2 deletions src/main/scala/firrtl/Emitter.scala
Original file line number Diff line number Diff line change
Expand Up @@ -685,13 +685,19 @@ class VerilogEmitter extends SeqTransform with Emitter {
emit(Seq("`ifdef RANDOMIZE_MEM_INIT"))
emit(Seq("`define RANDOMIZE"))
emit(Seq("`endif"))
emit(Seq("`ifndef RANDOM"))
emit(Seq("`define RANDOM $random"))
emit(Seq("`endif"))
emit(Seq("`ifdef RANDOMIZE"))
emit(Seq(" integer initvar;"))
emit(Seq(" initial begin"))
emit(Seq(" `ifdef INIT_RANDOM"))
emit(Seq(" `INIT_RANDOM"))
emit(Seq(" `endif"))
// This enables test benches to set the random values at time 0.001,
// then start the simulation later
// then start the simulation later
// Verilator does not support delay statements, so they are omitted.
emit(Seq(" `ifndef verilator"))
emit(Seq(" `ifndef VERILATOR"))
emit(Seq(" #0.002 begin end"))
emit(Seq(" `endif"))
for (x <- initials) emit(Seq(tab, x))
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