Add example design for Alveo U55N/C1100

Signed-off-by: Alex Forencich <alex@alexforencich.com>

README.md

@@ -21,6 +21,7 @@ Example designs are included for the following FPGA boards:
 *  Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 1SM21CHU1F53E1VG)
 *  Terasic DE10-Agilex (Intel Agilex F AGFB014R24B2E2V)
 *  Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)
+*  Xilinx Alveo U55N/Varium C1100 (Xilinx Virtex UltraScale+ XCU55N)
 *  Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200)
 *  Xilinx Alveo U250 (Xilinx Virtex UltraScale+ XCU250)
 *  Xilinx Alveo U280 (Xilinx Virtex UltraScale+ XCU280)

example/Alveo/fpga/README.md

@@ -8,6 +8,7 @@ The design implements the PCIe AXI lite master module, the PCIe AXI master modul
 
 * FPGA
   * AU50: xcu50-fsvh2104-2-e
+  * AU55N/C1100: xcu55n-fsvh2892-2L-e
   * AU200: xcu200-fsgd2104-2-e
   * AU250: xcu250-fsgd2104-2-e
   * AU280: xcu280-fsvh2892-2L-e

example/Alveo/fpga/fpga_AU55N/Makefile

@@ -0,0 +1,95 @@
+
+# FPGA settings
+FPGA_PART = xcu55n-fsvh2892-2L-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+# Files for synthesis
+SYN_FILES = rtl/fpga_au55.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/common/example_core_pcie_us.v
+SYN_FILES += rtl/common/example_core_pcie.v
+SYN_FILES += rtl/common/example_core.v
+SYN_FILES += rtl/common/axi_ram.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
+SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
+SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
+SYN_FILES += lib/pcie/rtl/pcie_msix.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
+SYN_FILES += lib/pcie/rtl/dma_psdpram.v
+SYN_FILES += lib/pcie/rtl/priority_encoder.v
+SYN_FILES += lib/pcie/rtl/pulse_merge.v
+
+# XDC files
+XDC_FILES = fpga_au55.xdc
+
+# IP
+IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+

example/Alveo/fpga/fpga_AU55N/config.tcl

@@ -0,0 +1,90 @@
+set params [dict create]
+
+# Board info
+set board_vendor_id [expr 0x10ee]
+set board_device_id [expr 0x9037]
+
+# PCIe IDs
+set pcie_vendor_id [expr 0x1234]
+set pcie_device_id [expr 0x0001]
+set pcie_class_code [expr 0x058000]
+set pcie_revision_id [expr 0x00]
+set pcie_subsystem_vendor_id $board_vendor_id
+set pcie_subsystem_device_id $board_device_id
+
+# BAR sizes
+dict set params BAR0_APERTURE "24"
+dict set params BAR2_APERTURE "24"
+dict set params BAR4_APERTURE "16"
+
+# PCIe IP core settings
+set pcie [get_ips pcie4c_uscale_plus_0]
+
+# Internal interface settings
+dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
+
+# configure BAR settings
+proc configure_bar {pcie pf bar aperture} {
+    set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
+    for { set i 0 } { $i < [llength $size_list] } { incr i } {
+        set scale [lindex $size_list $i]
+
+        if {$aperture > 0 && $aperture < ($i+1)*10} {
+            set size [expr 1 << $aperture - ($i*10)]
+
+            puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
+
+            set pcie_config [dict create]
+
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
+            dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
+
+            set_property -dict $pcie_config $pcie
+
+            return
+        }
+    }
+    puts "${pcie} PF${pf} BAR${bar}: disabled"
+    set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
+}
+
+# Configure BARs
+configure_bar $pcie 0 0 [dict get $params BAR0_APERTURE]
+configure_bar $pcie 0 2 [dict get $params BAR2_APERTURE]
+configure_bar $pcie 0 4 [dict get $params BAR4_APERTURE]
+
+# PCIe IP core configuration
+set pcie_config [dict create]
+
+# PCIe IDs
+dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
+dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
+dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
+dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
+dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
+
+# MSI-X
+dict set pcie_config "CONFIG.pf0_msi_enabled" {false}
+dict set pcie_config "CONFIG.pf0_msix_enabled" {true}
+dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" {01F}
+dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_5:4}
+dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00000000}
+dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_5:4}
+dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00008000}
+dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External}
+
+set_property -dict $pcie_config $pcie
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+# set_property generic $param_list [current_fileset]
+set_property generic $param_list [get_filesets sources_1]