2019年UPC应用物理专业《数字电子技术课程设计》任务内容:数字时钟设计
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Updated
Jul 2, 2019 - Verilog
2019年UPC应用物理专业《数字电子技术课程设计》任务内容:数字时钟设计
Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II
Arilla - a RISC-V based microcomputer system, with a PS2 mouse controller and 12-bit RGB SVGA graphics card, running Arilla Paint.
Logic Design.
Ejemplos de codigo con implementación en hardware para la tarjeta Cyclone IV lenguaje VHDL
DEUARC RISC computer design in Quartus II 13.0
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
The goal of ECE 385 course is to teach students to design, build, and test/debug a digital system, which can be a 16-bit microprocessor, a dedicated logic core, or a system-on-a-chip (SoC) platform
Implementações feitas em VHDL nas disciplinas de Circuitos Digitais I, Circuitos Digitais II e Sistemas Digitais Avançados
Projeto de uma ULA feito em Quartus II para a disciplina de Sistemas Digitais (2019.1)
Quartus II Pipelined Processor
A digital design implementation of a FIFO memory circuit using VHDL simulated in Quartus.
A 16 bit processor, following the RISC architecture. Made with Quartus and VHDL.
Icy Tower FPGA Cyclone III Game
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