SvdModel2LstmSDSoCV2-no-unroll

.gitignore

@@ -7,4 +7,12 @@ data/game_*
 data/windows*
 # Hardware Directories
 vivado_hls.log
-./hls/
+vitis_hls.log
+hls_prj/
+vivado/
+vitis_include/
+./token
+
+# PYNQ
+**/.ipynb_checkpoints
+**/sds_trace_data.dat

CMakeLists.txt

@@ -1,36 +1,53 @@
 cmake_minimum_required(VERSION 3.10)
 # Set the project name
 project(Svd VERSION 1.0)
-# Specify the C++ standard
-set(CMAKE_CXX_STANDARD 11)
-set(CMAKE_CXX_STANDARD_REQUIRED True)
 
-# To locate "custom"/manually added libraries
+# To locate "custom", i.e. manually added, libraries
 list(APPEND CMAKE_MODULE_PATH ${PROJECT_SOURCE_DIR}/cmake/Modules)
 
-# Locate libraries and headers (see Files in ./cmake/Modules/)
-# find_package(Vitis REQUIRED)
-find_package(Vivado REQUIRED)
-find_package(OpenCv REQUIRED)
+# Locate external libraries and headers (see Files in ./cmake/Modules/)
+# Search for HLS: if Vitis is found, use C++14, else fall back to C++11.
+find_package(Vitis REQUIRED)
+if (Vitis_FOUND)
+	# Specify the C++14 standard
+	message("[INFO] Vitis HLS FOUND.")
+	set(CMAKE_CXX_STANDARD 14)
+	set(CMAKE_CXX_STANDARD_REQUIRED True)
+	set(HLS_INCLUDE_DIRS ${VITIS_INCLUDE_DIRS})
+	add_compile_definitions(__VITIS_HLS__)
+else()
+	message("[INFO] Vivado HLS FOUND.")
+	find_package(Vivado REQUIRED)
+	# Specify the C++11 standard
+	set(CMAKE_CXX_STANDARD 11)
+	set(CMAKE_CXX_STANDARD_REQUIRED True)
+	set(HLS_INCLUDE_DIRS ${VIVADO_INCLUDE_DIRS})
+endif()
+# find_package(OpenCv REQUIRED)
 
-# set(HLS_INCLUDE_DIRS ${VITIS_INCLUDE_DIRS})
-# set(HLS_INCLUDE_DIRS ${VIVADO_INCLUDE_DIRS})
-# message(${HLS_INCLUDE_DIRS})
+message(${HLS_INCLUDE_DIRS})
 
 # Add all definitions
-if (WIN32)
-	add_compile_definitions(IMAGE_OUTPUT_PATH="C:/Users/ste/phd/hls_projects/hls_svd/data")
-else()
-	add_compile_definitions(IMAGE_OUTPUT_PATH="/mnt/c/Users/ste/phd/hls_projects/hls_svd/data")
-endif()
 # The following definitions is required for compiling half-precision numbers.
 add_compile_definitions(HLS_NO_XIL_FPO_LIB)
 # add_compile_definitions(USE_FLOAT)
 add_compile_definitions(DEBUG_LEVEL=2)
 
+add_compile_definitions(INPUT_SIZE=1024)
+add_compile_definitions(HIDDEN_SIZE=512)
+add_compile_definitions(NUM_GATES=4)
+add_compile_definitions(NUM_SAMPLES=2)
+add_compile_definitions(NUM_TILES_U=4)
+add_compile_definitions(NUM_ZERO_TILES_U=1)
+add_compile_definitions(NUM_TILES_V=4)
+add_compile_definitions(NUM_ZERO_TILES_V=1)
+add_compile_definitions(NUM_TIMESTEPS=28)
+add_compile_definitions(FIX_WIDTH=16)
+add_compile_definitions(FIX_FRACT_WIDTH=5)
+
 # Move executable in bin/, along side the DLLs (copied)
 set(EXECUTABLE_OUTPUT_PATH ${PROJECT_SOURCE_DIR}/bin)
-file(COPY ${OpenCv_LIBS} DESTINATION ${EXECUTABLE_OUTPUT_PATH})
+# file(COPY ${OpenCv_LIBS} DESTINATION ${EXECUTABLE_OUTPUT_PATH})
 
 # NOTE: an object file becomes a library. All libraries/objects must be LINKED later!
 # Tell the application where to find the other CMake config files.

README.md

@@ -47,17 +47,108 @@ cmake ..
 make all
 ```
 
+## Notes on Using Vitis
+
+### AXIS Interface and DMA
+
+Vitis to include the TLAST side channel if and only if TKEEP and TSTRB are also included.
+
+In order to attach the port to a Xilinx DMA, the TLAST signal must be properly set HIGH at the end of the data transmission.
+
+The TKEEP and TSTRB signals must be *always* set to HIGH, as indicated in the [AXIS documentation](https://developer.arm.com/documentation/ihi0051/a/Interface-Signals/Byte-qualifiers/TKEEP-and-TSTRB-combinations).
+
+
+### Partitioning hls::vector Arrays
+
+A standard way of partitioning an array is:
+```c++
+  hls::stream<hls::vector<int, 4> > x_streams[M][N];
+#pragma HLS ARRAY_PARTITION variable=x_streams complete dim=0
+```
+However, since we are dealing with a `hls::vector` type, setting `dim=0` (all dimensions) will partition the array on the vector dimension too.
+
+In the example above, Vitis will create `M * N * 4` different streams (instead of just `M * N`). To fix it, manually specify the partitioning on the dimensions, like so:
+```c++
+  hls::stream<hls::vector<int, 4> > x_streams[M][N];
+#pragma HLS ARRAY_PARTITION variable=x_streams complete dim=1
+#pragma HLS ARRAY_PARTITION variable=x_streams complete dim=2
+```
+
+### Implementing AXIS Interfaces
+
+In order to implement AXIS interfaces, avoid using `depth` in the pragma, as follows:
+```c++
+const int kAxiBitwidth = 128;
+
+void HlsVectorKernelU(hls::stream<ap_axiu<kAxiBitwidth, 0, 0, 0> >& x_port,
+                      hls::stream<ap_axiu<kAxiBitwidth, 0, 0, 0> >& y_port) {
+#pragma HLS INTERFACE axis port=x_port // depth=... <- DON'T SPECIFY THE DEPTH!
+#pragma HLS INTERFACE axis port=y_port // depth=... <- DON'T SPECIFY THE DEPTH!
+	// ...
+}
+```
+The type `ap_axiu` must now be used to generate AXIS with side channels. Note: for using external DMAs, we need the TLAST, TKEEP and TSTRB signals. In particular, TKEEP and TSTRB must be all set (i.e. all ones) in order to signal data packets.
+
+#### AxiStreamInterface Class
+
+This repository contains a wrapper class for kernel arguments of type `hls::stream` named `AxiStreamInterface`. The class is implemented following a _Policy-based_ C++ paradigm, meaning that it accepts either a `AxiStreamPort` or `AxiStreamFifo` as possible policies (in practice, a template argument).
+
+The idea is to have a kernel argument, i.e. an HLS port, which can be either an AXIS interface with side-channels, or a bare FIFO interface connected to another kernel. In fact, Vitis HLS doesn't allow stream interfaces with side-channels within an IP. To overcome the issue, the `AxiStreamInterface` can be customized to be an IP port or a FIFO port, depending on the use of the kernel.
+
+An example of this can be seen in `HlsKernelU` and in `svd::SvdKernel`, which specialize the `svd::KernelU` function template. In the first case, the `svd::KernelU` has its output stream port `xu_port` connected to one of the IP's ports (with side-channels). In the latter case instead, `svd::KernelU` is connected to `svd::KernelS`, and so its `xu_port` argument is an internal FIFO (without side-channels).
+
+The `AxiStreamInterface` class in `axis_lib.h` can also be used with `hls::vector` types.
+
+### HLS Vector Patch
+
+If the project will be compiled with the Vitis HLS libraries, it needs a patch in the `hls::vector` class.
+
+Simply add the following line in the `vector` class after the `public:` statement:
+```c++
+public:
+  static const int width = N;
+```
+
+In this way, one can access the number of elements in a `hls::vector` at compile/synthesis time by doing:
+
+```c++
+hls::vector<int, 5> a;
+std::cout << "Number of elements in a: " << a::width << std::endl;
+
+// > Number of elements in a: 5
+```
+
+## Notes on PYNQ Design
+
+### Vivado Project
+
+#### Xilinx DMA
+
+The DMA should be configured in the following way:
+
+* Max burst length to maximum
+* Register buffer width to maximum
+
+#### HP Ports
+
+All HP ports should be set to 64bit width (to avoid receiving data interleaved by zeroes).
+
+
 ## TODOs
 
 List of TODOs:
-	* Import u, s, v new kernels
-	* Import (and clean up?) u, s, v old kernels
-	* Import DMA functions
-	* Import and clean up HLS SVD-model-Bouganis
-	* Import and clean up HLS SVD-model-2LSTM
-	* Import some testbenches to try compile something
+
+	* ~Import u, s, v new kernels~
+	* ~Import (and clean up?) u, s, v old kernels~
+	* ~Import DMA functions~
+	* ~Import and clean up HLS SVD-model-Bouganis~
+	* ~Import and clean up HLS SVD-model-2LSTM~
+	* ~Import some testbenches to try compile something~
 
 ## Bugs
 
 List of possible bugs:
-* Having not squared images in games generates distorted images.
+
+* Constructing data handler storage might lead to segmentation faults.
+* Having `R == 1` might trigger some asserts.
+* Having `output_size == H` in HlsKernelV might break hardware runs.

cmake/Modules/FindVitis.cmake

@@ -1,11 +1,13 @@
 if (WIN32)
-	set(VITIS_INCLUDE_DIRS D:/Programs/Xilinx/Vitis_HLS/2020.2/include/)
+	# set(VITIS_INCLUDE_DIRS D:/Programs/Xilinx/Vitis_HLS/2021.1/include/)
+	set(VITIS_INCLUDE_DIRS C:/Users/ste/phd/hls_projects/hls_svd/vitis_include/2020.2/include/)
+	# set(VITIS_INCLUDE_DIRS C:/Users/ste/phd/hls_projects/hls_svd/vitis_include/2021.1/include/)
 else()
-	set(VITIS_INCLUDE_DIRS /mnt/d/Programs/Xilinx/Vitis_HLS/2020.2/include/)
+	set(VITIS_INCLUDE_DIRS /mnt/d/Programs/Xilinx/Vitis_HLS/2021.1/include/)
 endif()
 
 # NOTE: It handles the REQUIRED, QUIET and version-related arguments of find_package.
 # It also sets the <PackageName>_FOUND variable. The package is considered found
 # if all variables listed contain valid results, e.g. valid filepaths.
 include(FindPackageHandleStandardArgs)
-find_package_handle_standard_args(Vitis DEFAULT_MSG VITIS_INCLUDE_DIRS)
+find_package_handle_standard_args(Vitis DEFAULT_MSG VITIS_INCLUDE_DIRS)