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rejunity / z80-open-silicon Public

generated from TinyTapeout/tt07-verilog-template

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gds

Optional half cycle earlier MREQ, IORQ, RD, WR signals #58

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Optional half cycle earlier MREQ, IORQ, RD, WR signals

Optional half cycle earlier MREQ, IORQ, RD, WR signals #58

Summary
Jobs
- gds
- precheck
- gl_test
- viewer
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- Usage
- Workflow file

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Optional half cycle earlier MREQ, IORQ, RD, WR signals #58

gl_test

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