Skip to content
View flavian112's full-sized avatar

Block or report flavian112

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. internet_clock internet_clock Public

    A digital 7-segment clock, synced via internet.

  2. weather_station_sensor weather_station_sensor Public

    Weather Station Sensor

  3. riscv_cpu riscv_cpu Public

    My Attempt at writing a simple RISC-V CPU in Verilog.

    Verilog 1

  4. audio_amplifier audio_amplifier Public

    Audio pre- and poweramplifier, supplies

  5. signal_probe signal_probe Public

    Acquiring analog data via adc, transfer with dma, process, write to dac on a samd51.

    C++

  6. ethz_ddca ethz_ddca Public

    Digital Design and Computer Architecture, SAFARI ETHZ Course Notes.

    Verilog