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Merge pull request #11 from evka85/v3
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v3.8.0 -- Switched to the new OH FPGA communication protocol from Andrew, which uses 6b8b encoding and only one elink. Also added some GE2/1 support.
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@evka85
evka85 committed Feb 15, 2019
2 parents a7210c0 + 8dc9479 commit 3018fd2
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Showing 14 changed files with 986 additions and 257 deletions.
23 changes: 7 additions & 16 deletions common/hdl/gem_amc.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,8 @@ entity gem_amc is
g_NUM_TRIG_TX_LINKS : integer;

g_NUM_IPB_SLAVES : integer;
g_DAQ_CLK_FREQ : integer
g_DAQ_CLK_FREQ : integer;
g_SYSTEM : string := "GE11"
);
port(
reset_i : in std_logic;
Expand Down Expand Up @@ -169,8 +170,8 @@ architecture gem_amc_arch of gem_amc is
signal gbt_ic_tx_data_arr : t_std2_array(g_NUM_OF_OHs * 3 - 1 downto 0);
signal gbt_ic_rx_data_arr : t_std2_array(g_NUM_OF_OHs * 3 - 1 downto 0);
signal promless_tx_data : std_logic_vector(15 downto 0);
signal oh_fpga_tx_data_arr : t_std10_array(g_NUM_OF_OHs - 1 downto 0);
signal oh_fpga_rx_data_arr : t_std14_array(g_NUM_OF_OHs - 1 downto 0);
signal oh_fpga_tx_data_arr : t_std8_array(g_NUM_OF_OHs - 1 downto 0);
signal oh_fpga_rx_data_arr : t_std8_array(g_NUM_OF_OHs - 1 downto 0);
signal vfat3_tx_data_arr : t_vfat3_elinks_arr(g_NUM_OF_OHs - 1 downto 0);
signal vfat3_rx_data_arr : t_vfat3_elinks_arr(g_NUM_OF_OHs - 1 downto 0);

Expand Down Expand Up @@ -198,10 +199,7 @@ architecture gem_amc_arch of gem_amc is
signal vfat_mask_arr : t_std24_array(g_NUM_OF_OHs - 1 downto 0);

signal use_v3b_elink_mapping : std_logic;
signal v3b_slow_rx_bitshift : std_logic_vector(2 downto 0);
signal v3b_tx_0_bitslip : std_logic_vector(3 downto 0);
signal v3b_tx_1_bitslip : std_logic_vector(3 downto 0);


-- test module links
signal test_gbt_rx_data_arr : t_gbt_frame_array((g_NUM_OF_OHs * 3) - 1 downto 0);
signal test_gbt_tx_data_arr : t_gbt_frame_array((g_NUM_OF_OHs * 3) - 1 downto 0);
Expand Down Expand Up @@ -485,9 +483,6 @@ begin
use_oh_vfat3_connectors_o => use_oh_vfat3_connectors,
vfat3_sc_only_mode_o => vfat3_sc_only_mode,
use_v3b_elink_mapping_o => use_v3b_elink_mapping,
v3b_slow_rx_bitshift_o => v3b_slow_rx_bitshift,
v3b_tx_0_bitslip_o => v3b_tx_0_bitslip,
v3b_tx_1_bitslip_o => v3b_tx_1_bitslip,
manual_link_reset_o => manual_link_reset
);

Expand Down Expand Up @@ -601,9 +596,8 @@ begin
mgt_rx_data_arr_i => gt_gbt_rx_data_arr_i,
link_status_arr_o => gbt_link_status_arr
);


i_gbt_link_mux : entity work.gbt_link_mux

i_gbt_link_mux : entity work.gbt_link_mux(gbt_link_mux_ge21)
generic map(
g_NUM_OF_OHs => g_NUM_OF_OHs
)
Expand All @@ -617,9 +611,6 @@ begin
link_test_mode_i => loopback_gbt_test_en,
use_oh_vfat3_connectors_i => use_oh_vfat3_connectors,
use_v3b_mapping_i => use_v3b_elink_mapping,
v3b_slow_rx_bitshift_i => v3b_slow_rx_bitshift,
v3b_slow_tx_bitslip_0_i => v3b_tx_0_bitslip,
v3b_slow_tx_bitslip_1_i => v3b_tx_1_bitslip,

sca_tx_data_arr_i => sca_tx_data_arr,
sca_rx_data_arr_o => sca_rx_data_arr,
Expand Down
212 changes: 140 additions & 72 deletions common/hdl/misc/gbt_link_mux.vhd
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22 changes: 2 additions & 20 deletions common/hdl/misc/gem_system_regs.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -38,10 +38,7 @@ port(
loopback_gbt_test_en_o : out std_logic;
use_oh_vfat3_connectors_o : out std_logic;
use_v3b_elink_mapping_o : out std_logic;
v3b_slow_rx_bitshift_o : out std_logic_vector(2 downto 0);
v3b_tx_0_bitslip_o : out std_logic_vector(3 downto 0);
v3b_tx_1_bitslip_o : out std_logic_vector(3 downto 0);


vfat3_sc_only_mode_o : out std_logic;
manual_link_reset_o : out std_logic
);
Expand All @@ -68,10 +65,7 @@ architecture gem_system_regs_arch of gem_system_regs is
signal vfat3_sc_only_mode : std_logic;

signal use_v3b_elink_mapping : std_logic;
signal v3b_slow_rx_bitshift : std_logic_vector(2 downto 0);
signal v3b_tx_0_bitslip : std_logic_vector(3 downto 0);
signal v3b_tx_1_bitslip : std_logic_vector(3 downto 0);


--== LEGACY Firmware date and version (taken from GLIB) ==--
-- TODO: remove legacy firmware date and version once the software is ready
constant c_legacy_sys_ver_year :integer range 0 to 99 :=17;
Expand Down Expand Up @@ -131,9 +125,6 @@ begin

vfat3_sc_only_mode_o <= vfat3_sc_only_mode;
use_v3b_elink_mapping_o <= use_v3b_elink_mapping;
v3b_slow_rx_bitshift_o <= v3b_slow_rx_bitshift;
v3b_tx_0_bitslip_o <= v3b_tx_0_bitslip;
v3b_tx_1_bitslip_o <= v3b_tx_1_bitslip;

--===============================================================================================
-- this section is generated by <gem_amc_repo_root>/scripts/generate_registers.py (do not edit)
Expand Down Expand Up @@ -193,9 +184,6 @@ begin
regs_read_arr(6)(REG_GEM_SYSTEM_VFAT3_USE_OH_VFAT3_SLOTS_BIT) <= use_oh_vfat3_connectors;
regs_read_arr(6)(REG_GEM_SYSTEM_VFAT3_SC_ONLY_MODE_BIT) <= vfat3_sc_only_mode;
regs_read_arr(6)(REG_GEM_SYSTEM_VFAT3_USE_OH_V3B_MAPPING_BIT) <= use_v3b_elink_mapping;
regs_read_arr(6)(REG_GEM_SYSTEM_VFAT3_V3B_FPGA_SLOW_RX_BITSHIFT_MSB downto REG_GEM_SYSTEM_VFAT3_V3B_FPGA_SLOW_RX_BITSHIFT_LSB) <= v3b_slow_rx_bitshift;
regs_read_arr(6)(REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_0_BITSLIP_MSB downto REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_0_BITSLIP_LSB) <= v3b_tx_0_bitslip;
regs_read_arr(6)(REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_1_BITSLIP_MSB downto REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_1_BITSLIP_LSB) <= v3b_tx_1_bitslip;
regs_read_arr(9)(REG_GEM_SYSTEM_TESTS_GBT_LOOPBACK_EN_BIT) <= loopback_gbt_test_en;
regs_read_arr(10)(REG_GEM_SYSTEM_LEGACY_SYSTEM_BOARD_ID_MSB downto REG_GEM_SYSTEM_LEGACY_SYSTEM_BOARD_ID_LSB) <= legacy_board_id;
regs_read_arr(11)(REG_GEM_SYSTEM_LEGACY_SYSTEM_SYSTEM_ID_MSB downto REG_GEM_SYSTEM_LEGACY_SYSTEM_SYSTEM_ID_LSB) <= legacy_sys_id;
Expand All @@ -208,9 +196,6 @@ begin
use_oh_vfat3_connectors <= regs_write_arr(6)(REG_GEM_SYSTEM_VFAT3_USE_OH_VFAT3_SLOTS_BIT);
vfat3_sc_only_mode <= regs_write_arr(6)(REG_GEM_SYSTEM_VFAT3_SC_ONLY_MODE_BIT);
use_v3b_elink_mapping <= regs_write_arr(6)(REG_GEM_SYSTEM_VFAT3_USE_OH_V3B_MAPPING_BIT);
v3b_slow_rx_bitshift <= regs_write_arr(6)(REG_GEM_SYSTEM_VFAT3_V3B_FPGA_SLOW_RX_BITSHIFT_MSB downto REG_GEM_SYSTEM_VFAT3_V3B_FPGA_SLOW_RX_BITSHIFT_LSB);
v3b_tx_0_bitslip <= regs_write_arr(6)(REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_0_BITSLIP_MSB downto REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_0_BITSLIP_LSB);
v3b_tx_1_bitslip <= regs_write_arr(6)(REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_1_BITSLIP_MSB downto REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_1_BITSLIP_LSB);
loopback_gbt_test_en <= regs_write_arr(9)(REG_GEM_SYSTEM_TESTS_GBT_LOOPBACK_EN_BIT);

-- Connect write pulse signals
Expand All @@ -230,9 +215,6 @@ begin
regs_defaults(6)(REG_GEM_SYSTEM_VFAT3_USE_OH_VFAT3_SLOTS_BIT) <= REG_GEM_SYSTEM_VFAT3_USE_OH_VFAT3_SLOTS_DEFAULT;
regs_defaults(6)(REG_GEM_SYSTEM_VFAT3_SC_ONLY_MODE_BIT) <= REG_GEM_SYSTEM_VFAT3_SC_ONLY_MODE_DEFAULT;
regs_defaults(6)(REG_GEM_SYSTEM_VFAT3_USE_OH_V3B_MAPPING_BIT) <= REG_GEM_SYSTEM_VFAT3_USE_OH_V3B_MAPPING_DEFAULT;
regs_defaults(6)(REG_GEM_SYSTEM_VFAT3_V3B_FPGA_SLOW_RX_BITSHIFT_MSB downto REG_GEM_SYSTEM_VFAT3_V3B_FPGA_SLOW_RX_BITSHIFT_LSB) <= REG_GEM_SYSTEM_VFAT3_V3B_FPGA_SLOW_RX_BITSHIFT_DEFAULT;
regs_defaults(6)(REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_0_BITSLIP_MSB downto REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_0_BITSLIP_LSB) <= REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_0_BITSLIP_DEFAULT;
regs_defaults(6)(REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_1_BITSLIP_MSB downto REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_1_BITSLIP_LSB) <= REG_GEM_SYSTEM_VFAT3_V3B_FPGA_TX_1_BITSLIP_DEFAULT;
regs_defaults(9)(REG_GEM_SYSTEM_TESTS_GBT_LOOPBACK_EN_BIT) <= REG_GEM_SYSTEM_TESTS_GBT_LOOPBACK_EN_DEFAULT;

-- Define writable regs
Expand Down
108 changes: 108 additions & 0 deletions common/hdl/oh/link/6b8b.vhd
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Original file line number Diff line number Diff line change
@@ -0,0 +1,108 @@
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.sixbit_eightbit_pkg.all;

entity sixbit_eightbit is
port(
clock : in std_logic;
l1a : in std_logic;
bc0 : in std_logic;
resync : in std_logic;
idle : in std_logic;
header : in std_logic;
sixbit : in std_logic_vector (5 downto 0);
eightbit : out std_logic_vector (7 downto 0)
);

end sixbit_eightbit;

architecture Behavioral of sixbit_eightbit is
begin

process (clock) begin
if (rising_edge(clock)) then

-- make sure ttc commands have priority
if (l1a='1') then eightbit <= L1A_CHAR;
elsif (bc0='1') then eightbit <= BC0_CHAR;
elsif (resync='1') then eightbit <= RESYNC_CHAR;
elsif (idle='1') then eightbit <= IDLE_CHAR;
elsif (header='1') then eightbit <= HEADER_CHAR;
else
case sixbit is
when "000000" => eightbit <= "01011001";
when "000001" => eightbit <= "01110001";
when "000010" => eightbit <= "01110010";
when "000011" => eightbit <= "11000011";
when "000100" => eightbit <= "01100101";
when "000101" => eightbit <= "11000101";
when "000110" => eightbit <= "11000110";
when "000111" => eightbit <= "10000111";
when "001000" => eightbit <= "01101001";
when "001001" => eightbit <= "11001001";
when "001010" => eightbit <= "11001010";
when "001011" => eightbit <= "10001011";
when "001100" => eightbit <= "11001100";
when "001101" => eightbit <= "10001101";
when "001110" => eightbit <= "10001110";
when "001111" => eightbit <= "01001011";
when "010000" => eightbit <= "01010011";
when "010001" => eightbit <= "11010001";
when "010010" => eightbit <= "11010010";
when "010011" => eightbit <= "10010011";
when "010100" => eightbit <= "11010100";
when "010101" => eightbit <= "10010101";
when "010110" => eightbit <= "10010110";
when "010111" => eightbit <= "00010111";
when "011000" => eightbit <= "11011000";
when "011001" => eightbit <= "10011001";
when "011010" => eightbit <= "10011010";
when "011011" => eightbit <= "00011011";
when "011100" => eightbit <= "10011100";
when "011101" => eightbit <= "00011101";
when "011110" => eightbit <= "00011110";
when "011111" => eightbit <= "01011100";
when "100000" => eightbit <= "01100011";
when "100001" => eightbit <= "11100001";
when "100010" => eightbit <= "11100010";
when "100011" => eightbit <= "10100011";
when "100100" => eightbit <= "11100100";
when "100101" => eightbit <= "10100101";
when "100110" => eightbit <= "10100110";
when "100111" => eightbit <= "00100111";
when "101000" => eightbit <= "11101000";
when "101001" => eightbit <= "10101001";
when "101010" => eightbit <= "10101010";
when "101011" => eightbit <= "00101011";
when "101100" => eightbit <= "10101100";
when "101101" => eightbit <= "00101101";
when "101110" => eightbit <= "00101110";
when "101111" => eightbit <= "01101100";
when "110000" => eightbit <= "01110100";
when "110001" => eightbit <= "10110001";
when "110010" => eightbit <= "10110010";
when "110011" => eightbit <= "00110011";
when "110100" => eightbit <= "10110100";
when "110101" => eightbit <= "00110101";
when "110110" => eightbit <= "00110110";
when "110111" => eightbit <= "01010110";
when "111000" => eightbit <= "10111000";
when "111001" => eightbit <= "00111001";
when "111010" => eightbit <= "00111010";
when "111011" => eightbit <= "01011010";
when "111100" => eightbit <= "00111100";
when "111101" => eightbit <= "01001101";
when "111110" => eightbit <= "01001110";
when "111111" => eightbit <= "01100110";
when others => eightbit <= "00000000";
end case;
end if;

end if;
end process;

end Behavioral;

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