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Update Documentation
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Teddy-van-Jerry committed Mar 15, 2024
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2 changes: 1 addition & 1 deletion Cargo.lock

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2 changes: 1 addition & 1 deletion Cargo.toml
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Expand Up @@ -3,7 +3,7 @@ name = "pytv"
description = "Python Templated Verilog"
repository = "https://github.com/autohdw/pytv"
authors = ["Teddy van Jerry <me@teddy-van-jerry.org>"]
version = "0.1.0"
version = "0.1.1"
readme = "README.md"
license = "GPL-3.0-or-later"
keywords = ["verilog", "python", "template", "generation"]
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14 changes: 12 additions & 2 deletions README.md
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@@ -1,14 +1,24 @@
# pytv
Python Templated Verilog

## Packages
The package is available on [crates.io](https://crates.io/crates/pytv).
## Package
The package `pytv` is available on [crates.io](https://crates.io/crates/pytv).
Documentation is available on [docs.rs](https://docs.rs/pytv).

To use the package, run
```sh
cargo add pytv
```

# Related Auto Generator Projects
- **FLAMES**: template-based C++ library for Vitis HLS
[[website](https://flames.autohdw.com)]
[[GitHub](https://github.com/autohdw/flames)]
[[paper at IEEE](https://ieeexplore.ieee.org/document/10437992)]
[[paper PDF](https://wqzhao.org/assets/zhao2024flexible.pdf)]
- **AHDW**: a DSL, the predecessor of this project
[[paper at IEEE](https://ieeexplore.ieee.org/document/10396119)]
[[paper PDF](https://wqzhao.org/assets/zhao2023automatic.pdf)]

## Author
[Teddy van Jerry](https://github.com/Teddy-van-Jerry) ([Wuqiong Zhao](https://wqzhao.org))
2 changes: 1 addition & 1 deletion src/convert.rs
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Expand Up @@ -3,7 +3,7 @@ use crate::FileOptions;
use std::io::{Result, Write};
use std::path;

/// The `Convert` struct represents a converter that converts PYTV script to Python script to generate Verilog.
/// Represents a converter that converts PYTV script to Python script to generate Verilog.
///
/// It is also possible to run the Python script after conversion and optionally delete it after running it.
/// It contains methods for converting code and managing input/output files.
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17 changes: 17 additions & 0 deletions src/lib.rs
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//! Python Templated Verilog
//!
//! # Generation Process
//! `.pytv` --> `.v.py` --> `.py`
//!
//! # Examples
//! To be added.
//!
//! # Related Auto Generator Projects
//! - **FLAMES**: template-based C++ library for Vitis HLS
//! [[website](https://flames.autohdw.com)]
//! [[GitHub](https://github.com/autohdw/flames)]
//! [[paper at IEEE](https://ieeexplore.ieee.org/document/10437992)]
//! [[paper PDF](https://wqzhao.org/assets/zhao2024flexible.pdf)]
//! - **AHDW**: a DSL, the predecessor of this project
//! [[paper at IEEE](https://ieeexplore.ieee.org/document/10396119)]
//! [[paper PDF](https://wqzhao.org/assets/zhao2023automatic.pdf)]
mod config;
mod convert;

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