Fix INST Indentation Bug

Also fix the option preamble_py bug.
autohdw · Apr 6, 2024 · 88d419e · 88d419e
1 parent 25af867
commit 88d419e
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Showing 6 changed files with 62 additions and 37 deletions.
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -3,7 +3,7 @@ name = "pytv"
 description = "Python Templated Verilog"
 repository = "https://github.com/autohdw/pytv"
 authors = ["Teddy van Jerry <me@teddy-van-jerry.org>"]
-version = "0.5.1"
+version = "0.5.2"
 readme = "README.md"
 license = "GPL-3.0-or-later"
 keywords = ["verilog", "python", "template", "generation"]

diff --git a/examples/test.pytv b/examples/test.pytv
@@ -21,22 +21,24 @@ Do nothing here either! { some content }
 //! dyn_parameters = []
 //! for i in range(2):
 //!     dyn_parameters.append((f"name{i+10}", i + 10))
-//! <INST>
-//! module: test
-//! name: inst_test
-//! vparams:
-//!   N: 8
-//!   !mystery: dyn_vparams
-//!   M: `value_M`
-//! parameters:
-//!   name1: value1
-//!   name2: value2
-//!   name`1+2`: `a`
-//!   !other_parameters: dyn_parameters
-//! ports:
-//!   port1: net1
-//!   !other_name: dyn_ports
-//! </INST>
+//! if 1 + 1 == 2:
+//!     <INST>
+//!     module: test
+//!     name: inst_test
+//!     vparams:
+//!       N: 8
+//!       !mystery: dyn_vparams
+//!       M: `value_M`
+//!     parameters:
+//!       name1: value1
+//!       name2: value2
+//!       name`1+2`: `a`
+//!       !other_parameters: dyn_parameters
+//!     ports:
+//!       port1: net1
+//!       !other_name: dyn_ports
+//!     </INST>
+//! #
 wire x;
 assign x = y;
 

diff --git a/src/config.rs b/src/config.rs
@@ -84,8 +84,8 @@ struct Args {
     #[arg(short, long = "var", value_name = "KEY=VAL")]
     vars: Vec<String>,
     /// Preamble Python file
-    #[arg(short, long = "preamble", value_name = "FILE", required = false)]
-    preamble_py: String
+    #[arg(short, long = "preamble", value_name = "FILE")]
+    preamble_py: Option<String>
 }
 
 impl Config {
@@ -140,11 +140,7 @@ impl Config {
                 output: args.output,
             },
             vars.ok(),
-            if args.preamble_py.is_empty() {
-                None
-            } else {
-                Some(args.preamble_py)
-            }
+            args.preamble_py,
         )
     }
 

diff --git a/src/convert.rs b/src/convert.rs
@@ -249,6 +249,8 @@ impl Convert {
         let magic_string_len = 2 + self.config.magic_comment_str.len();
         #[cfg(feature = "inst")]
         let mut within_inst = false;
+        #[cfg(feature = "inst")]
+        let mut inst_indent_space = 0usize;
         let mut inst_str = String::new();
         #[cfg(feature = "inst")]
         // print user-defined variables
@@ -301,6 +303,7 @@ impl Convert {
                         &mut stream,
                         &mut within_inst,
                         &mut inst_str,
+                        &mut inst_indent_space,
                     )?;
                     #[cfg(not(feature = "inst"))]
                     self.process_python_line(&line, 0, &mut stream)?;
@@ -327,6 +330,7 @@ impl Convert {
                         &mut stream,
                         &mut within_inst,
                         &mut inst_str,
+                        &mut inst_indent_space,
                     )?;
                     #[cfg(not(feature = "inst"))]
                     self.process_python_line(&line, py_indent_prior, &mut stream)?;

diff --git a/src/inst.rs b/src/inst.rs
@@ -27,23 +27,32 @@ impl Convert {
         stream: &mut W,
         within_inst: &mut bool,
         inst_str: &mut String,
+        inst_indent_space: &mut usize,
     ) -> Result<(), Box<dyn Error>> {
         match self.inst_state(line) {
             InstState::Begin => {
+                // calculate the space before the <INST>
+                // and print the Python code before the <INST>
+                let all_space = &line.len() - line.trim_start().len();
+                if all_space < py_indent_prior {
+                    return Err("Indentation error: <INST> is not properly indented.".into());
+                }
+                *inst_indent_space = all_space - py_indent_prior;
                 if *within_inst {
                     return Err("Nested <INST> is not allowed.".into());
                 }
                 *within_inst = true;
-                writeln!(stream, "print('// INST')")?;
+                writeln!(stream, "{}print('// INST')", " ".repeat(*inst_indent_space))?;
             }
             InstState::End => {
                 if !*within_inst {
                     return Err("Encountering </INST> with no <INST> to end.".into());
                 }
                 *within_inst = false;
-                self.print_inst(stream, inst_str)?;
+                self.print_inst(stream, inst_str, *inst_indent_space)?;
                 inst_str.clear();
                 writeln!(stream, "print('// END of INST')")?;
+                *inst_indent_space = 0;
             }
             _ => {
                 let useful_str = utf8_slice::from(&line, py_indent_prior);
@@ -71,16 +80,25 @@ impl Convert {
         re.replace_all(inst_str, "__group_$1:$2\n").to_string()
     }
 
-    fn inst_group_print_to_dot_inst(inst_str: &str) -> String {
+    fn inst_group_print_to_dot_inst(inst_str: &str, inst_indent_space: usize) -> String {
         let re = Regex::new(r"__group_\w+:\s*(.*)[\r\n$]").unwrap();
         re.replace_all(
             inst_str,
-            "''')\n_inst_file.write(f'{_inst_var_map($1)}')\n_inst_file.write(f'''",
+            format!(
+                "''')\n{}_inst_file.write(f'{{_inst_var_map($1)}}')\n{}_inst_file.write(f'''",
+                " ".repeat(inst_indent_space),
+                " ".repeat(inst_indent_space)
+            ),
         )
         .to_string()
     }
 
-    fn print_inst<W: Write>(&self, stream: &mut W, inst_str: &str) -> Result<(), Box<dyn Error>> {
+    fn print_inst<W: Write>(
+        &self,
+        stream: &mut W,
+        inst_str: &str,
+        inst_indent_space: usize,
+    ) -> Result<(), Box<dyn Error>> {
         let inst_map: serde_yaml::Value =
             serde_yaml::from_str(&self.apply_protected_verilog_regex(
                 Self::apply_protected_inst_group_regex(inst_str).as_str(),
@@ -89,9 +107,10 @@ impl Convert {
         inst_str_parsed = Self::inst_group_print_to_dot_inst(
             self.undo_protected_brackets(inst_str_parsed.as_str())
                 .as_str(),
+            inst_indent_space,
         );
         // print to .inst
-        writeln!(stream, "_inst_file.write(f'''{}''')", inst_str_parsed)?;
+        writeln!(stream, "{}_inst_file.write(f'''{}''')", " ".repeat(inst_indent_space), inst_str_parsed)?;
         // print to .v
         match inst_map["module"].as_str() {
             Some(module) => writeln!(
@@ -128,8 +147,12 @@ impl Convert {
                             } else {
                                 ","
                             },
-                            self.escape_single_quote(self.undo_protected_brackets(key_str).as_str()),
-                            self.escape_single_quote(self.undo_protected_brackets(value_str).as_str())
+                            self.escape_single_quote(
+                                self.undo_protected_brackets(key_str).as_str()
+                            ),
+                            self.escape_single_quote(
+                                self.undo_protected_brackets(value_str).as_str()
+                            )
                         )?;
                     }
                 } else {