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\documentclass{article} | ||
\usepackage{cite} | ||
\usepackage[hidelinks]{hyperref} | ||
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\newcommand{\pytvversion}{0.5.6} | ||
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\title{PyTV: Python Templated Verilog} | ||
\author{Wuqiong Zhao} | ||
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\begin{document} | ||
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\maketitle | ||
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\begin{abstract} | ||
PyTV (Python Templated Verilog)% | ||
\footnote{This is the documentation to PyTV version \texttt{\pytvversion{}}.} | ||
is a Rust library and binary tool that extends Verilog with Python templating. | ||
\end{abstract} | ||
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\tableofcontents | ||
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\section{Introduction}\label{sec:introduction} | ||
\input{sections/introduction} | ||
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\section{Installation}\label{sec:installation} | ||
\input{sections/installation} | ||
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\section{Syntax Specifications}\label{sec:syntax} | ||
\input{sections/syntax} | ||
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\bibliographystyle{IEEEtran} | ||
\phantomsection | ||
\addcontentsline{toc}{section}{References} | ||
\bgroup | ||
\small | ||
\bibliography{IEEEabrv, ref} | ||
\egroup | ||
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\end{document} |
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% Templated languages | ||
One method of auto generation of parameterized hardware relies on templated languages. | ||
AHDW \cite{zhao2023automatic} is a language building upon Verilog with custom syntax for parameterized hardware. | ||
% PyTV's advantage | ||
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% PyTV project information | ||
PyTV is open-source at \url{https://github.com/autohdw/pytv} | ||
and is distributed under the GPL-3.0 license. | ||
The Rust crate is available at \url{https://crates.io/crates/pytv}. |
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