Pipelined-MIPS

MIPS Pipelined CPU simulation using VHDL language

DOCS

Name		Name	Last commit message	Last commit date
Latest commit History 103 Commits
report		report
.gitignore		.gitignore
1op.mem		1op.mem
ALU.vhd		ALU.vhd
ALU_PortA.vhd		ALU_PortA.vhd
ALU_PortB.vhd		ALU_PortB.vhd
ALU_Src1_MUX.vhd		ALU_Src1_MUX.vhd
ALU_Src2_MUX.vhd		ALU_Src2_MUX.vhd
BufferMemory.vhdl		BufferMemory.vhdl
CompileEveryThing.do		CompileEveryThing.do
EX_Buffer.vhd		EX_Buffer.vhd
Execute_Stage.vhd		Execute_Stage.vhd
Forwarding_Unit.vhd		Forwarding_Unit.vhd
ID_EX.vhd		ID_EX.vhd
IR.txt		IR.txt
MemoryStage.vhdl		MemoryStage.vhdl
Mux21.vhdl		Mux21.vhdl
Mux41.vhdl		Mux41.vhdl
NEW_CPU_MAIN.vhd		NEW_CPU_MAIN.vhd
README.md		README.md
Ram.vhdl		Ram.vhdl
Register.vhdl		Register.vhdl
SomeNotes.txt		SomeNotes.txt
TriState.vhdl		TriState.vhdl
TriStateSP.vhdl		TriStateSP.vhdl
WBStage.vhdl		WBStage.vhdl
_CPU_MAIN.vhd		_CPU_MAIN.vhd
assembler_new.py		assembler_new.py
control_unit.vhd		control_unit.vhd
decode_stage.vhd		decode_stage.vhd
fetch_buffer.vhd		fetch_buffer.vhd
fetch_stage.vhd		fetch_stage.vhd
hazard_detection.vhd		hazard_detection.vhd
ins_ram.vhd		ins_ram.vhd
maindofile.txt		maindofile.txt
my_adder.vhd		my_adder.vhd
my_nadder.vhd		my_nadder.vhd
new_fetch_buffer.vhd		new_fetch_buffer.vhd
new_fetch_stage.vhd		new_fetch_stage.vhd
one_operand.txt		one_operand.txt
register.vhd		register.vhd
register_file.vhd		register_file.vhd
register_onebit.vhd		register_onebit.vhd
sign_extend.vhd		sign_extend.vhd
test.vhd		test.vhd
underdstand.txt		underdstand.txt
zero_extend.vhd		zero_extend.vhd