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  1. ddr5_phy ddr5_phy Public

    DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

    SystemVerilog 41 22

  2. elevator-controller elevator-controller Public

    VHDL RTL Design, Verification, and FPGA Implementation of an Elevator Controller

    VHDL

  3. washing-machine-controller washing-machine-controller Public

    Verilog HDL implementation and verification of a controller unit of washing machine.

    Verilog

  4. AES-128 AES-128 Public

    RTL implementation of the AES algorithm with 128-bit key using Verilog.

    Verilog

  5. QPSK-Communication-System-Modeling QPSK-Communication-System-Modeling Public

    A MATLAB implementation for quadrature phase-shift keying communication system.

    MATLAB 2

  6. SnakeGame SnakeGame Public

    This project is done using C++, SFML library, and OOP concepts.

    C++