vitis
Here are 91 public repositories matching this topic...
This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.
-
Updated
Jan 8, 2024 - C
Docker container containing the Vitis 2023.2 tools & PetaLinux
-
Updated
Apr 8, 2024 - Dockerfile
-
Updated
Apr 19, 2021 - C++
🏄 Custom IP for vector operations
-
Updated
Aug 31, 2024 - VHDL
Example workflow project for firmware development in Vitis.
-
Updated
Feb 19, 2023 - C
A TFTP server running on Zynq-7000
-
Updated
May 15, 2024 - C
Vince's Vitis workspace for RSDecoder. Platform, system, and application for the RSDecoder hardware
-
Updated
Aug 28, 2020 - C
language server and vim plugin for xilinx vivado and vitis
-
Updated
Sep 16, 2024 - Vim Script
Baremetal C application that displays encoder values on a serial interface, starting from a Vivado block design and transitioning to a Vitis application.
-
Updated
Jun 11, 2024 - C
BSc Thesis: Design of Sound Source Localization System Based on FPGA and MEMS Microphone
-
Updated
Aug 13, 2024 - VHDL
-
Updated
Dec 24, 2022 - C
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
-
Updated
Dec 3, 2023 - C
🔖 Downgrade to 2019.2
-
Updated
Dec 25, 2023 - Shell
Improve this page
Add a description, image, and links to the vitis topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the vitis topic, visit your repo's landing page and select "manage topics."