T20 Cricket Game using Verilog coding. Includes a constraint file for implementing on Nexys A7 FPGA board.
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Updated
Dec 23, 2023 - Verilog
T20 Cricket Game using Verilog coding. Includes a constraint file for implementing on Nexys A7 FPGA board.
A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.
A WIP RISC-V CPU implementation. Right now I'm working on implementing RV32I.
A collection of code from CDA 4240C: Design of Digital System and Lab
Pipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board
This accelerator uses a Nexys A7 100T FPGA to overlay an one image over another using an image mask and performing masking operations, with the results being displayed over VGA. The purpose of this project was to utilize the parallel nature of FPGAs to create a hardware accelerator for image masking applications.
(Your Own Digital Accelerator) A Smoothing filter by using a Finite Impulse Response (FIR) and a Low Pass Filter (LPF) algorithm. The hardware used is a NEXYS A7 Field Programmable Gate Array (FPGA) programmedin Verilog.
Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details.
Example of how to get started with olofk/fusesoc.
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