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VHDL-2008 initialization not handled #11

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trayres opened this issue Sep 13, 2018 · 0 comments
Open

VHDL-2008 initialization not handled #11

trayres opened this issue Sep 13, 2018 · 0 comments

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@trayres
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trayres commented Sep 13, 2018

signal douta_ram0 : std_logic_vector(31 downto 0) := 32D"0";

Lines like this return:

syntax error, unexpected NAME at "D" in line 82.

Is there a way to handle the VHDL-2008 init of signals by adding a rule for it?
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@trayres