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00001-add-stm32mp157a-sodimm2-mx.patch
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00001-add-stm32mp157a-sodimm2-mx.patch
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diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4c3ba0468276..f82f1e9824b8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -30,6 +30,7 @@ DTC_FLAGS_stm32mp157c-ev1-a7-examples += -@
DTC_FLAGS_stm32mp157c-ev1-m4-examples += -@
DTC_FLAGS_stm32mp157f-ev1-a7-examples += -@
DTC_FLAGS_stm32mp157f-ev1-m4-examples += -@
+DTC_FLAGS_stm32mp157a-sodimm2-mx += -@
dtb-$(CONFIG_ARCH_ALPINE) += \
alpine-db.dtb
@@ -1118,7 +1119,8 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157f-ev1-a7-examples.dtb \
stm32mp157f-ev1-m4-examples.dtb \
stm32mp157c-lxa-mc1.dtb \
- stm32mp157c-odyssey.dtb
+ stm32mp157c-odyssey.dtb \
+ stm32mp157a-sodimm2-mx.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157a-sodimm2-mx.dts b/arch/arm/boot/dts/stm32mp157a-sodimm2-mx.dts
new file mode 100644
index 000000000000..2867c4d45923
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-sodimm2-mx.dts
@@ -0,0 +1,1509 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Author: STM32CubeMX code generation for STMicroelectronics.
+ */
+
+/* For more information on Device Tree configuration, please refer to
+ * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
+ */
+
+/dts-v1/;
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xa.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include "stm32mp15-m4-srm.dtsi"
+
+/* USER CODE BEGIN includes */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/stm32-hdp.h>
+/* USER CODE END includes */
+
+/ {
+ model = "STMicroelectronics STM32MP157AAA3 SODIMM module";
+ compatible = "st,stm32mp157a-sodimm2-mx", "st,stm32mp157";
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x40000000>;
+
+ /* USER CODE BEGIN memory */
+ /* USER CODE END memory */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* USER CODE BEGIN reserved-memory */
+
+ mcuram2:mcuram2@10000000{
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0:vdev0vring0@10040000{
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1:vdev0vring1@10041000{
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer:vdev0buffer@10042000{
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcu_rsc_table:mcu_rsc_table@10048000{
+ compatible = "shared-dma-pool";
+ reg = <0x10048000 0x8000>;
+ no-map;
+ };
+
+ mcuram:mcuram@30000000{
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram:retram@38000000{
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ gpu_reserved:gpu@f6000000{
+ reg = <0xf6000000 0x8000000>;
+ no-map;
+ };
+ /* USER CODE END reserved-memory */
+ };
+
+ /* USER CODE BEGIN root */
+
+ aliases{
+ serial0 = &uart4;
+ ethernet0 = ðernet0;
+ spi0 = &qspi;
+ display0 = &lcd0;
+ //serial1 = &usart3;
+ };
+
+ reg_5v_host: reg-5v-host {
+ compatible = "regulator-fixed";
+ regulator-name = "5v-host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_5v_power_pins_mx>;
+ pinctrl-1 = <&usb_5v_power_sleep_pins_mx>;
+ //gpio = <&gpioi 11 GPIO_ACTIVE_HIGH>; //power USB port
+ enable-active-high;
+ default-on;
+ status = "okay";
+ };
+
+ reg_5v_otg: reg-5v-otg {
+ compatible = "regulator-fixed";
+ regulator-name = "5v-otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_otg_5v_power_pins_mx>;
+ pinctrl-1 = <&usb_otg_5v_power_sleep_pins_mx>;
+ //gpio = <&gpioc 13 GPIO_ACTIVE_HIGH>; //power for second port
+ enable-active-high;
+ default-on;
+ status = "okay";
+ };
+
+ reg_3v3_rgb: regulator-3v3-rgb {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3-rgb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpiog 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ status = "okay";
+ };
+
+ rgb_panel_backlight: rgb-panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ default-off;
+ linux,default-trigger = "backlight";
+ status = "okay";
+ };
+
+ lcd0: display {
+ compatible = "out4,o4-lcd5-800-480", "panel-dpi";
+ label = "display";
+ power-supply = <®_3v3_rgb>;
+ backlight = <&rgb_panel_backlight>;
+ //bits-per-pixel = <32>;
+ //bus-width = <24>;
+ //connector-type = <17>;
+
+ status = "okay";
+
+ port {
+ dsi_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ // panel-timing {
+ // clock-frequency = <33000000>;
+ // hactive = <800>;
+ // vactive = <480>;
+ // hfront-porch = <40>;
+ // hback-porch = <40>;
+ // hsync-len = <43>;
+ // vback-porch = <29>;
+ // vfront-porch = <13>;
+ // vsync-len = <3>;
+ // hsync-active = <0>;
+ // vsync-active = <0>;
+ // de-active = <1>;
+ // pixelclk-active = <1>;
+ // };
+
+ };
+
+ led {
+ compatible = "gpio-leds";
+ status = "okay";
+
+ // for test external i2c GPIO expander
+ green1 {
+ label = "heartbeat";
+ gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+
+ // for test external i2c GPIO expander
+ green2 {
+ label = "network";
+ gpios = <&pcf8574a 7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "netdev";
+ default-state = "on";
+ };
+ };
+
+ vin:vin{
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ chosen{
+ stdout-path = "serial0:115200n8";
+ };
+
+
+ usb_phy_tuning:usb-phy-tuning{
+ st,hs-dc-level = <2>;
+ st,fs-rftime-tuning;
+ st,hs-rftime-reduction;
+ st,hs-current-trim = <15>;
+ st,hs-impedance-trim = <1>;
+ st,squelch-level = <3>;
+ st,hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+ };
+ /* USER CODE END root */
+
+ clocks {
+ /* USER CODE BEGIN clocks */
+
+ clk_ext_camera:clk-ext-camera{
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ /* USER CODE END clocks */
+
+#ifndef CONFIG_TFABOOT
+ clk_lsi: clk-lsi {
+ clock-frequency = <32000>;
+ };
+ clk_hsi: clk-hsi {
+ clock-frequency = <64000000>;
+ };
+ clk_csi: clk-csi {
+ clock-frequency = <4000000>;
+ };
+ clk_lse: clk-lse {
+ clock-frequency = <32768>;
+ };
+ clk_hse: clk-hse {
+ clock-frequency = <24000000>;
+ };
+#endif /*CONFIG_TFABOOT*/
+ };
+
+}; /*root*/
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+
+ dcmi_pins_mx: dcmi_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
+ <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
+ <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
+ <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
+ <STM32_PINMUX('H', 8, AF13)>, /* DCMI_HSYNC */
+ <STM32_PINMUX('H', 9, AF13)>, /* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>, /* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>, /* DCMI_D2 */
+ <STM32_PINMUX('H', 12, AF13)>, /* DCMI_D3 */
+ <STM32_PINMUX('H', 14, AF13)>, /* DCMI_D4 */
+ <STM32_PINMUX('I', 4, AF13)>; /* DCMI_D5 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_mx: dcmi_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, ANALOG)>, /* DCMI_PIXCLK */
+ <STM32_PINMUX('B', 7, ANALOG)>, /* DCMI_VSYNC */
+ <STM32_PINMUX('B', 8, ANALOG)>, /* DCMI_D6 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* DCMI_D7 */
+ <STM32_PINMUX('H', 8, ANALOG)>, /* DCMI_HSYNC */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>, /* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>, /* DCMI_D2 */
+ <STM32_PINMUX('H', 12, ANALOG)>, /* DCMI_D3 */
+ <STM32_PINMUX('H', 14, ANALOG)>, /* DCMI_D4 */
+ <STM32_PINMUX('I', 4, ANALOG)>; /* DCMI_D5 */
+ };
+ };
+
+ eth1_pins_mx: eth1_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RX_CLK */
+ <STM32_PINMUX('A', 7, AF11)>, /* ETH1_RX_CTL */
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH1_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH1_RXD3 */
+ <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('B', 11, AF11)>, /* ETH1_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH1_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH1_TXD3 */
+ <STM32_PINMUX('G', 4, AF11)>, /* ETH1_GTX_CLK */
+ <STM32_PINMUX('G', 5, AF11)>, /* ETH1_CLK125 */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ eth1_sleep_pins_mx: eth1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RX_CLK */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_RX_CTL */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH1_RXD2 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH1_RXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_CTL */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH1_TXD2 */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH1_TXD3 */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH1_GTX_CLK */
+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH1_CLK125 */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
+ };
+ };
+
+ fdcan1_pins_mx: fdcan1_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 13, AF9)>; /* FDCAN1_TX */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 9, AF9)>; /* FDCAN1_RX */
+ bias-pull-up;
+ };
+ };
+
+ fdcan1_sleep_pins_mx: fdcan1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* FDCAN1_TX */
+ <STM32_PINMUX('I', 9, ANALOG)>; /* FDCAN1_RX */
+ };
+ };
+
+ fdcan2_pins_mx: fdcan2_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 13, AF9)>; /* FDCAN2_TX */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF9)>; /* FDCAN2_RX */
+ bias-pull-up;
+ };
+ };
+
+ fdcan2_sleep_pins_mx: fdcan2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, ANALOG)>, /* FDCAN2_RX */
+ <STM32_PINMUX('B', 13, ANALOG)>; /* FDCAN2_TX */
+ };
+ };
+
+ i2c2_pins_mx: i2c2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins_mx: i2c2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c5_pins_mx: i2c5_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, AF4)>, /* I2C5_SDA */
+ <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_mx: i2c5_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* I2C5_SDA */
+ <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SCL */
+ };
+ };
+
+ ltdc_pins_mx: ltdc_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 6, AF14)>, /* LTDC_HSYNC */
+ <STM32_PINMUX('I', 13, AF14)>, /* LTDC_VSYNC */
+ <STM32_PINMUX('I', 15, AF14)>, /* LTDC_R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* LTDC_R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* LTDC_R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* LTDC_R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* LTDC_R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* LTDC_R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* LTDC_R6 */
+ <STM32_PINMUX('J', 6, AF14)>, /* LTDC_R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* LTDC_G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* LTDC_G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* LTDC_G2 */
+ <STM32_PINMUX('J', 10, AF14)>, /* LTDC_G3 */
+ <STM32_PINMUX('J', 11, AF14)>, /* LTDC_G4 */
+ <STM32_PINMUX('J', 12, AF14)>, /* LTDC_B0 */
+ <STM32_PINMUX('J', 13, AF14)>, /* LTDC_B1 */
+ <STM32_PINMUX('J', 14, AF14)>, /* LTDC_B2 */
+ <STM32_PINMUX('J', 15, AF14)>, /* LTDC_B3 */
+ <STM32_PINMUX('K', 0, AF14)>, /* LTDC_G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* LTDC_G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* LTDC_G7 */
+ <STM32_PINMUX('K', 3, AF14)>, /* LTDC_B4 */
+ <STM32_PINMUX('K', 4, AF14)>, /* LTDC_B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* LTDC_B6 */
+ <STM32_PINMUX('K', 6, AF14)>, /* LTDC_B7 */
+ <STM32_PINMUX('K', 7, AF14)>; /* LTDC_DE */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 14, AF14)>; /* LTDC_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_sleep_pins_mx: ltdc_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* LTDC_HSYNC */
+ <STM32_PINMUX('I', 13, ANALOG)>, /* LTDC_VSYNC */
+ <STM32_PINMUX('I', 14, ANALOG)>, /* LTDC_CLK */
+ <STM32_PINMUX('I', 15, ANALOG)>, /* LTDC_R0 */
+ <STM32_PINMUX('J', 0, ANALOG)>, /* LTDC_R1 */
+ <STM32_PINMUX('J', 1, ANALOG)>, /* LTDC_R2 */
+ <STM32_PINMUX('J', 2, ANALOG)>, /* LTDC_R3 */
+ <STM32_PINMUX('J', 3, ANALOG)>, /* LTDC_R4 */
+ <STM32_PINMUX('J', 4, ANALOG)>, /* LTDC_R5 */
+ <STM32_PINMUX('J', 5, ANALOG)>, /* LTDC_R6 */
+ <STM32_PINMUX('J', 6, ANALOG)>, /* LTDC_R7 */
+ <STM32_PINMUX('J', 7, ANALOG)>, /* LTDC_G0 */
+ <STM32_PINMUX('J', 8, ANALOG)>, /* LTDC_G1 */
+ <STM32_PINMUX('J', 9, ANALOG)>, /* LTDC_G2 */
+ <STM32_PINMUX('J', 10, ANALOG)>, /* LTDC_G3 */
+ <STM32_PINMUX('J', 11, ANALOG)>, /* LTDC_G4 */
+ <STM32_PINMUX('J', 12, ANALOG)>, /* LTDC_B0 */
+ <STM32_PINMUX('J', 13, ANALOG)>, /* LTDC_B1 */
+ <STM32_PINMUX('J', 14, ANALOG)>, /* LTDC_B2 */
+ <STM32_PINMUX('J', 15, ANALOG)>, /* LTDC_B3 */
+ <STM32_PINMUX('K', 0, ANALOG)>, /* LTDC_G5 */
+ <STM32_PINMUX('K', 1, ANALOG)>, /* LTDC_G6 */
+ <STM32_PINMUX('K', 2, ANALOG)>, /* LTDC_G7 */
+ <STM32_PINMUX('K', 3, ANALOG)>, /* LTDC_B4 */
+ <STM32_PINMUX('K', 4, ANALOG)>, /* LTDC_B5 */
+ <STM32_PINMUX('K', 5, ANALOG)>, /* LTDC_B6 */
+ <STM32_PINMUX('K', 6, ANALOG)>, /* LTDC_B7 */
+ <STM32_PINMUX('K', 7, ANALOG)>; /* LTDC_DE */
+ };
+ };
+
+ quadspi_pins_mx: quadspi_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, AF10)>, /* QUADSPI_BK1_NCS */
+ <STM32_PINMUX('C', 0, AF10)>; /* QUADSPI_BK2_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins3 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('G', 7, AF11)>, /* QUADSPI_BK2_IO3 */
+ <STM32_PINMUX('G', 10, AF11)>, /* QUADSPI_BK2_IO2 */
+ <STM32_PINMUX('H', 2, AF9)>, /* QUADSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, AF9)>; /* QUADSPI_BK2_IO1 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ quadspi_sleep_pins_mx: quadspi_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>, /* QUADSPI_BK1_NCS */
+ <STM32_PINMUX('C', 0, ANALOG)>, /* QUADSPI_BK2_NCS */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 10, ANALOG)>, /* QUADSPI_CLK */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* QUADSPI_BK2_IO3 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QUADSPI_BK2_IO2 */
+ <STM32_PINMUX('H', 2, ANALOG)>, /* QUADSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, ANALOG)>; /* QUADSPI_BK2_IO1 */
+ };
+ };
+
+ sdmmc1_pins_mx: sdmmc1_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins3 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc2_pins_mx: sdmmc2_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('D', 3, AF9)>, /* SDMMC2_D7 */
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('D', 3, AF9)>, /* SDMMC2_D7 */
+ <STM32_PINMUX('E', 5, AF9)>; /* SDMMC2_D6 */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins3 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('D', 3, ANALOG)>, /* SDMMC2_D7 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ uart4_pins_mx: uart4_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ uart4_sleep_pins_mx: uart4_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* UART4_RX */
+ <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ };
+
+ usb_otg_hs_pins_mx: usb_otg_hs_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* USB_OTG_HS_ID */
+ };
+ };
+
+ usb_otg_hs_sleep_pins_mx: usb_otg_hs_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* USB_OTG_HS_ID */
+ };
+ };
+
+ /* USER CODE BEGIN pinctrl */
+ usb_5v_power_pins_mx: usb_5v_power_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('I', 11, GPIO)>, /* USB_POWER_EN */
+ <STM32_PINMUX('I', 8, GPIO)>; /* USB_POWER_EN */
+ bias-disable;
+ output-high;
+ };
+ };
+
+ usb_5v_power_sleep_pins_mx: usb_5v_power_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('I', 11, GPIO)>, /* USB_POWER_EN */
+ <STM32_PINMUX('I', 8, GPIO)>; /* USB_POWER_EN */
+ bias-disable;
+ output-low;
+ };
+ };
+
+ usb_otg_5v_power_pins_mx: usb_otg_5v_power_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 13, GPIO)>; /* USB_POWER_EN */
+ bias-disable;
+ output-high;
+ };
+ };
+
+ usb_otg_5v_power_sleep_pins_mx: usb_otg_5v_power_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 13, GPIO)>; /* USB_POWER_EN */
+ bias-disable;
+ output-low;
+ };
+ };
+
+ /* USER CODE END pinctrl */
+};
+
+&pinctrl_z {
+ u-boot,dm-pre-reloc;
+
+ i2c4_pins_z_mx: i2c4_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c4_sleep_pins_z_mx: i2c4_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
+ };
+ };
+
+ /* USER CODE BEGIN pinctrl_z */
+ /* USER CODE END pinctrl_z */
+};
+
+&m4_rproc{
+ /*Restriction: "memory-region" property is not managed - please to use User-Section if needed*/
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ status = "okay";
+
+ /* USER CODE BEGIN m4_rproc */
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>, <&mcu_rsc_table>;
+ interrupt-parent = <&exti>;
+ interrupts = <68 1>;
+ wakeup-source;
+ /* USER CODE END m4_rproc */
+};
+
+&adc{
+ status = "okay";
+
+ /* USER CODE BEGIN adc */
+ /* USER CODE END adc */
+};
+
+&bsec{
+ status = "okay";
+
+ /* USER CODE BEGIN bsec */
+ /* USER CODE END bsec */
+};
+
+&crc1{
+ status = "okay";
+
+ /* USER CODE BEGIN crc1 */
+ /* USER CODE END crc1 */
+};
+
+&dcmi{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmi_pins_mx>;
+ pinctrl-1 = <&dcmi_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN dcmi */
+
+ port{
+
+ dcmi_0:endpoint{
+ remote-endpoint = <&ov5640_0>;
+ bus-type = <5>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ pclk-max-frequency = <77000000>;
+ };
+ };
+ /* USER CODE END dcmi */
+};
+
+&dma1{
+ status = "okay";
+
+ /* USER CODE BEGIN dma1 */
+ sram = <&dma_pool>;
+ /* USER CODE END dma1 */
+};
+
+&dma2{
+ status = "okay";
+
+ /* USER CODE BEGIN dma2 */
+ sram = <&dma_pool>;
+ /* USER CODE END dma2 */
+};
+
+&dmamux1{
+ status = "okay";
+
+ dma-masters = <&dma1 &dma2>;
+ dma-channels = <16>;
+
+ /* USER CODE BEGIN dmamux1 */
+ /* USER CODE END dmamux1 */
+};
+
+&dts{
+ status = "okay";
+
+ /* USER CODE BEGIN dts */
+ /* USER CODE END dts */
+};
+
+ðernet0{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <ð1_pins_mx>;
+ pinctrl-1 = <ð1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN ethernet0 */
+ phy-mode = "rgmii-id";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+ nvmem-cells = <ðernet_mac_address>;
+ nvmem-cell-names = "mac-address";
+
+ mdio0{
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0:ethernet-phy@0{
+ reg = <0>;
+ };
+ };
+ /* USER CODE END ethernet0 */
+};
+
+&gpu{
+ status = "okay";
+
+ /* USER CODE BEGIN gpu */
+ contiguous-area = <&gpu_reserved>;
+ /* USER CODE END gpu */
+};
+
+&hash1{
+ u-boot,dm-pre-reloc;
+ status = "okay";
+
+ /* USER CODE BEGIN hash1 */
+ /* USER CODE END hash1 */
+};
+
+&hsem{
+ status = "okay";
+
+ /* USER CODE BEGIN hsem */
+ /* USER CODE END hsem */
+};
+
+&i2c2{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_mx>;
+ pinctrl-1 = <&i2c2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c2 */
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+
+
+ ov5640:camera@3c{
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ DOVDD-supply = <&v2v8>;
+ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
+ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ rotation = <180>;
+ status = "okay";
+
+ port{
+
+ ov5640_0:endpoint{
+ remote-endpoint = <&dcmi_0>;
+ bus-width = <8>;
+ data-shift = <2>;
+ hsync-active = <0>;