code/coherence: the main chisel repository for coherence, where the DSL compiler is embeded as part of the code generation processcode/riscv-new: the repository of the RISC-V core used in the projectcode/chisel-testers2: the repository of a modified chisel-tester2 dependencies to support strong enum, a later official version may be useddriver: includes the Linux driver that we use to move data to and from the host to the FPGA and create interface for accessing the predictable cache on the FPGA.benchmarks: includes the benchmarks and utilities that we use. Note that thread management and file IO management is inbenchmarks/riscv-splash2, and the splash-2 benchmarks are inbenchmarks/parsec-3.0.runtime: includes the runtime library for the FPGA board. You can find the runtime library atruntime/fpga/software/runtime/wheremake compileshould create a binary file inruntime/fpga/build/vu9p/Vtp, which is used byrun.shto run programs. Note that an emulated design is includedruntime/fpga/software/emulation/, and it can be used together with qemu.qemu: includes the patch required to emulate the PCI-e device in qemu as well as useful scripts to launch the VM.synth: includes scripts and designs used in Vivado to perform synthesis.
The kernel version we use is 4.19.114 and the the OS version we use is Ubuntu 18.04.5. The FPGA used is the VCU1525.