diff --git a/Cargo.lock b/Cargo.lock
index f7fdaf2..1ee35d0 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -128,7 +128,7 @@ dependencies = [
 
 [[package]]
 name = "pytv"
-version = "0.1.0"
+version = "0.1.1"
 dependencies = [
  "clap",
  "regex",
diff --git a/Cargo.toml b/Cargo.toml
index f4b5898..3e3e18c 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -3,7 +3,7 @@ name = "pytv"
 description = "Python Templated Verilog"
 repository = "https://github.com/autohdw/pytv"
 authors = ["Teddy van Jerry <me@teddy-van-jerry.org>"]
-version = "0.1.0"
+version = "0.1.1"
 readme = "README.md"
 license = "GPL-3.0-or-later"
 keywords = ["verilog", "python", "template", "generation"]
diff --git a/README.md b/README.md
index 2208e07..f2f8c74 100644
--- a/README.md
+++ b/README.md
@@ -1,8 +1,8 @@
 # pytv
 Python Templated Verilog
 
-## Packages
-The package is available on [crates.io](https://crates.io/crates/pytv).
+## Package
+The package `pytv` is available on [crates.io](https://crates.io/crates/pytv).
 Documentation is available on [docs.rs](https://docs.rs/pytv).
 
 To use the package, run
@@ -10,5 +10,15 @@ To use the package, run
 cargo add pytv
 ```
 
+# Related Auto Generator Projects
+- **FLAMES**: template-based C++ library for Vitis HLS
+  [[website](https://flames.autohdw.com)]
+  [[GitHub](https://github.com/autohdw/flames)]
+  [[paper at IEEE](https://ieeexplore.ieee.org/document/10437992)]
+  [[paper PDF](https://wqzhao.org/assets/zhao2024flexible.pdf)]
+- **AHDW**: a DSL, the predecessor of this project
+  [[paper at IEEE](https://ieeexplore.ieee.org/document/10396119)]
+  [[paper PDF](https://wqzhao.org/assets/zhao2023automatic.pdf)]
+
 ## Author
 [Teddy van Jerry](https://github.com/Teddy-van-Jerry) ([Wuqiong Zhao](https://wqzhao.org))
diff --git a/src/convert.rs b/src/convert.rs
index 7763360..1739413 100644
--- a/src/convert.rs
+++ b/src/convert.rs
@@ -3,7 +3,7 @@ use crate::FileOptions;
 use std::io::{Result, Write};
 use std::path;
 
-/// The `Convert` struct represents a converter that converts PYTV script to Python script to generate Verilog.
+/// Represents a converter that converts PYTV script to Python script to generate Verilog.
 ///
 /// It is also possible to run the Python script after conversion and optionally delete it after running it.
 /// It contains methods for converting code and managing input/output files.
diff --git a/src/lib.rs b/src/lib.rs
index 36007be..6815ed8 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,3 +1,20 @@
+//! Python Templated Verilog
+//! 
+//! # Generation Process
+//! `.pytv` --> `.v.py` --> `.py`
+//! 
+//! # Examples
+//! To be added.
+//! 
+//! # Related Auto Generator Projects
+//! - **FLAMES**: template-based C++ library for Vitis HLS
+//!   [[website](https://flames.autohdw.com)]
+//!   [[GitHub](https://github.com/autohdw/flames)]
+//!   [[paper at IEEE](https://ieeexplore.ieee.org/document/10437992)]
+//!   [[paper PDF](https://wqzhao.org/assets/zhao2024flexible.pdf)]
+//! - **AHDW**: a DSL, the predecessor of this project
+//!   [[paper at IEEE](https://ieeexplore.ieee.org/document/10396119)]
+//!   [[paper PDF](https://wqzhao.org/assets/zhao2023automatic.pdf)]
 mod config;
 mod convert;